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| Integrated Mixed-Signal Solutions STAC9750/51 Value-Line Two-Channel AC'97 Codecs with Headphone Drive and SPDIF Output Value-Line Two-Channel AC'97 Codecs with Headphone Drive and SPDIF Output Data Sheet Revision 5.3 2-9750-D1- 5.3-0604 STAC9750/51 Value-Line Two-Channel AC'97 Codecs with Headphone Drive and SPDIF Output 1. TABLE OF CONTENTS 1. TABLE OF CONTENTS ............................................................................................................. 2 1.1. List of Figures ....................................................................................................................................5 1.2. List of Tables ......................................................................................................................................5 2. PRODUCT BRIEF ...................................................................................................................... 7 2.1. Features .............................................................................................................................................7 2.2. Description .........................................................................................................................................7 2.3. Ordering Information ..........................................................................................................................8 2.4. STAC9750/51 Block Diagram ...........................................................................................................9 2.5. Key Specifications ..............................................................................................................................9 2.6. Related Materials ...............................................................................................................................9 2.7. Additional Support ..............................................................................................................................9 3. CHARACTERISTICS/SPECIFICATIONS ................................................................................10 3.1. Electrical Specifications ...................................................................................................................10 3.1.1. Absolute Maximum Ratings: ..............................................................................................10 3.1.2. Recommended Operating Conditions ...............................................................................10 3.1.3. Power Consumption . .........................................................................................................10 3.1.4. Revision Comparision ........................................................................................................11 3.1.5. AC-Link Static Digital Specifications ..................................................................................12 3.1.6. STAC9750 Analog Performance Characteristics ...............................................................12 3.1.7. STAC9751 Analog Performance Characteristics ...............................................................13 3.2. AC Timing Characteristics ...............................................................................................................15 3.2.1. Cold Reset .........................................................................................................................15 3.2.2. Warm Reset .......................................................................................................................15 3.2.3. Clocks ................................................................................................................................16 3.2.4. Data Setup and Hold ..........................................................................................................17 3.2.5. Signal Rise and Fall Times ................................................................................................17 3.2.6. AC-Link Low Power Mode Timing ......................................................................................18 3.2.7. ATE Test Mode ..................................................................................................................18 4. TYPICAL CONNECTION DIAGRAM .......................................................................................19 5. AC-LINK ...................................................................................................................................20 5.1. Clocking ...........................................................................................................................................20 5.2. Reset ................................................................................................................................................20 6. DIGITAL INTERFACE ..............................................................................................................21 6.1. AC-Link Digital Serial Interface Protocol ..........................................................................................21 6.1.1. AC-Link Audio Output Frame (SDATA_OUT) ....................................................................22 6.1.1.1. Slot 1: Command Address Port ........................................................................23 6.1.1.2. Slot 2: Command Data Port ..............................................................................23 6.1.1.3. Slot 3: PCM Playback Left Channel ..................................................................23 6.1.1.4. Slot 4: PCM Playback Right Channel ...............................................................23 6.1.1.5. Slot 5: Reserved ...............................................................................................24 6.1.1.6. Slot 6: PCM Center Channel ............................................................................24 6.1.1.7. Slot 7: PCM Left Surround Channel .................................................................24 6.1.1.8. Slot 8: PCM Right Surround Channel ...............................................................24 6.1.1.9. Slot 9: PCM Low Frequency Channel ...............................................................24 Copyright (c) 2002 SigmaTel, Inc. All rights reserved. All contents of this document are protected by copyright law and may not be reproduced without the express written consent of SigmaTel, Inc. SigmaTel, the SigmaTel logo, and combinations thereof are trademarks of SigmaTel, Inc. Other product names used in this publication are for identification purposes only and may be trademarks or registered trademarks of their respective companies. The contents of this document are provided in connection with SigmaTel, Inc. products. SigmaTel, Inc. has made best efforts to ensure that the information contained herein is accurate and reliable. However, SigmaTel, Inc. makes no warranties, express or implied, as to the accuracy or completeness of the contents of this publication and is providing this publication "AS IS". SigmaTel, Inc. reserves the right to make changes to specifications and product descriptions at any time without notice, and to discontinue or make changes to its products at any time without notice. SigmaTel, Inc. does not assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential, or incidental damages. 2 2-9750-D1- 5.3-0604 STAC9750/51 Value-Line Two-Channel AC'97 Codecs with Headphone Drive and SPDIF Output 6.1.1.10. Slot 10: PCM Alternate Left ............................................................................24 6.1.1.11. Slot 11: PCM Alternate Right ..........................................................................24 6.1.1.12. Slot 12: Reserved ...........................................................................................24 6.1.2. AC-Link Audio Input Frame (SDATA_IN) ...........................................................................25 6.1.2.1. Slot 1: Status Address Port ...............................................................................26 6.1.2.2. Slot 2: Status Data Port ....................................................................................26 6.1.2.3. Slot 3: PCM Record Left Channel .....................................................................26 6.1.2.4. Slot 4: PCM Record Right Channel ..................................................................27 6.1.2.5. Slot 5: Reserved ...............................................................................................27 6.1.2.6. Slot 6: PCM Left Record Channel ....................................................................27 6.1.2.7. Slot 7: PCM Left Record Channel ....................................................................27 6.1.2.8. Slot 8: PCM Right Record Channel .................................................................27 6.1.2.9. Slot 9: PCM Right Record Channel .................................................................27 6.1.2.10. Slot 10: PCM Left Record Channel ................................................................28 6.1.2.11. Slot 11: PCM Right Record Channel .............................................................28 6.1.2.12. Slot 12: Reserved ..........................................................................................28 6.2. AC-Link Low Power Mode ...............................................................................................................28 6.3. Waking up the AC-Link ....................................................................................................................29 7. STAC9750/51 MIXER ..............................................................................................................30 7.1. Analog Mixer Input ...........................................................................................................................32 7.2. Analog Mixer Output ........................................................................................................................32 7.3. SPDIF Digital Mux ............................................................................................................................32 7.4. PC Beep Implementation .................................................................................................................32 7.5. Programming Registers ...................................................................................................................33 7.5.1. Reset (00h) ........................................................................................................................34 7.5.2. Play Master Volume Registers (Index 02h, 04h, and 06h) .................................................34 7.5.2.1. Master Volume (02h) ........................................................................................34 7.5.2.2. Headphone Out Volume (04h) ..........................................................................34 7.5.2.3. Master Volume MONO (06h) ............................................................................35 7.5.3. PC Beep Mixer Volume (Index 0Ah) ..................................................................................35 7.5.4. Analog Mixer Input Gain Registers (Index 0Ch - 18h) .......................................................36 7.5.4.1. Phone Mixer Volume (0Ch) ..............................................................................36 7.5.4.2. Mic Mixer Volume (0Eh) ...................................................................................36 7.5.4.3. Line In Mixer Volume (10h) ...............................................................................36 7.5.4.4. CD Mixer Volume (12h) ....................................................................................36 7.5.4.5. Video Mixer Volume (14h) ................................................................................37 7.5.4.6. AUX Mixer Volume (16h) ..................................................................................37 7.5.4.7. PCM Out Mixer Volume (18h) ...........................................................................37 7.5.5. Record Select (1Ah) ...........................................................................................................37 7.5.6. Record Gain (1Ch) .............................................................................................................38 7.5.7. General Purpose (20h) .......................................................................................................38 7.5.8. 3D Control (22h) .................................................................................................................39 7.5.9. Audio Interrupt (24h) ..........................................................................................................39 7.5.10. Powerdown Ctrl/Stat (26h) ...............................................................................................40 7.5.10.1. Ready Status ..................................................................................................40 7.5.10.2. Powerdown Controls .......................................................................................41 7.5.10.3. External Amplifier Power Down Control ..........................................................41 7.5.11. Extended Audio ID (28h) ..................................................................................................41 7.5.12. Extended Audio Control/Status (2Ah) ..............................................................................42 7.5.12.1. Variable Rate Sampling Enable ......................................................................42 7.5.12.2. SPDIF .............................................................................................................43 7.5.12.3. SPCV (SPDIF Configuration Valid) .................................................................43 7.5.12.4. SPSA1, SPSA0 (SPDIF Slot Assignment) ......................................................43 7.5.13. PCM DAC Rate Registers (2Ch and 32h) ........................................................................44 7.5.14. PCM DAC Rate (2Ch) ......................................................................................................44 7.5.15. PCM LR ADC Rate (32h) .................................................................................................44 7.5.16. SPDIF Control (3Ah) ........................................................................................................45 2-9750-D1- 5.3-0604 3 STAC9750/51 Value-Line Two-Channel AC'97 Codecs with Headphone Drive and SPDIF Output 7.5.17. Extended Modem Status and Control Register (3Eh) (Used in Revision CC1 and beyond) 46 7.5.18. GPIO Pin Configuration Register (4Ch) (Used in Revision CC1 and beyond) .................46 7.5.19. GPIO Pin Polarity/Type Register (4Eh)(Used in Revision CC1 and beyond) ...................46 7.5.20. GPIO Pin Sticky Register (50h) (Used in Revision CC1 and beyond) .............................47 7.5.21. GPIO Pin Mask Register (52h)(Used in Revision CC1 and beyond) ...............................47 7.5.22. GPIO Pin Status Register (54h) (Used in Revision CC1 and beyond) .............................48 7.5.23. Digital Audio Control (6Ah) ...............................................................................................48 7.5.24. Revision Code (6Ch) ........................................................................................................49 7.5.25. Analog Special (6Eh) .......................................................................................................49 7.5.25.1. ALL MIX ..........................................................................................................49 7.5.25.2. ADC Data on AC LINK ....................................................................................50 7.5.25.3. MuteFix Disable (Used in Revision CC1 and beyond) ....................................50 7.5.25.4. Mic Boost Select .............................................................................................50 7.5.25.5. Supply Override Select ...................................................................................50 7.5.25.6. 72h Enable (70h) ............................................................................................50 7.5.25.7. Analog Current Adjust (72h) ...........................................................................51 7.5.25.8. Internal Power-On/Off Anti-Pop Circuit ...........................................................51 7.5.26. GPIO Access Register (74h) (Used only in CA3 revision for GPIO) ................................52 7.5.27. High Pass Filter Bypass (Index 76h and 78h) ..................................................................52 7.5.27.1. 78h Enable (76h) ............................................................................................52 7.5.27.2. ADC High Pass FIlter Bypass(78h) ................................................................53 7.5.28. Vendor ID1 and ID2 (Index 7Ch and 7Eh) .......................................................................53 7.5.28.1. Vendor ID1 (7Ch) ............................................................................................53 7.5.28.2. Vendor ID2 76xx (7Eh) ...................................................................................53 8. LOW POWER MODES ............................................................................................................54 9. MULTIPLE CODEC SUPPORT ...............................................................................................56 9.1. Primary/Secondary Codec Selection ...............................................................................................56 9.1.1. Primary Codec Operation ...................................................................................................56 9.1.2. Secondary Codec Operation ..............................................................................................56 9.2. Secondary Codec Register Access Definitions ................................................................................57 10. TESTABILITY ........................................................................................................................58 11. PIN DESCRIPTION ................................................................................................................59 11.1. Digital I/O .......................................................................................................................................60 11.2. Analog I/O ......................................................................................................................................61 11.3. Filter/References/GPIO ..................................................................................................................62 11.4. Power and Ground Signals ............................................................................................................62 12. PACKAGE DRAWING ..........................................................................................................63 13. APPENDIX A: SPLIT INDEPENDENT POWER SUPPLY OPERATION ..............................64 14. APPENDIX B: PROGRAMMING REGISTERS .....................................................................66 15. DOCUMENT HISTORY ..........................................................................................................67 4 2-9750-D1- 5.3-0604 STAC9750/51 Value-Line Two-Channel AC'97 Codecs with Headphone Drive and SPDIF Output 1.1. List of Figures Figure 1. STAC9750/51 Block Diagram ...........................................................................................................9 Figure 2. Cold Reset Timing ..........................................................................................................................15 Figure 3. Warm Reset Timing ........................................................................................................................15 Figure 4. Clocks Timing .................................................................................................................................16 Figure 5. Data Setup and Hold Timing ...........................................................................................................17 Figure 6. Signal Rise and Fall Times Timing ..................................................................................................17 Figure 7. AC-Link Low Power Mode Timing ...................................................................................................18 Figure 8. ATE Test Mode Timing ...................................................................................................................18 Figure 9. STAC9751 Typical Connection Diagram ........................................................................................19 Figure 10. AC-Link to its Companion Controller .............................................................................................20 Figure 11. AC'97 Standard Bi-directional Audio Frame .................................................................................21 Figure 12. AC-Link Audio Output Frame ........................................................................................................22 Figure 13. Start of an Audio Output Frame ....................................................................................................22 Figure 14. STAC9750/51 Audio Input Frame .................................................................................................25 Figure 15. Start of an Audio Input Frame .......................................................................................................26 Figure 16. STAC9750/51 Powerdown Timing ................................................................................................28 Figure 17. STAC9750 2-Channel Mixer Functional Diagram .........................................................................31 Figure 18. STAC9751 2-Channel Mixer Functional Diagram .........................................................................31 Figure 19. Example of STAC9750/51 Powerdown/Powerup flow ..................................................................54 Figure 20. STAC9750/51 Powerdown/Powerup flow with analog still alive ...................................................55 Figure 21. STAC9750/51 Pin Description Drawing ........................................................................................59 Figure 22. 48-Pin TQFP Package Drawing ....................................................................................................63 Figure 23. STAC9750/51 Split Independent Power Supply Operation Typical Connection Diagram ............65 1.2. List of Tables Table 1. Recommended Operating Conditions. .............................................................................................10 Table 2. Power Consumption .........................................................................................................................10 Table 3. AC-Link Static Specifications ...........................................................................................................12 Table 4. STAC9750 Analog Performance Characteristics .............................................................................12 Table 5. STAC9751 Analog Performance Characteristics .............................................................................13 Table 6. Cold Reset Specifications ................................................................................................................15 Table 7. Warm Reset Specifications ..............................................................................................................15 Table 8. Clocks Specifications .......................................................................................................................16 Table 9. Clock mode configuration .................................................................................................................16 Table 10. Data Setup and Hold Specifications ...............................................................................................17 Table 11. Signal Rise and Fall Times Specifications .....................................................................................17 Table 12. AC-Link Low Power Mode Timing Specifications ...........................................................................18 Table 13. ATE Test Mode Specifications .......................................................................................................18 Table 14. STAC9750/51 Available Data Streams ..........................................................................................21 Table 15. Command Address Port Bit Assignments ......................................................................................23 Table 16. Command Data Port Bit Assignments ............................................................................................23 Table 17. Status Address Port Bit Assignments .............................................................................................26 Table 18. Status Data Port Bit Assignments ..................................................................................................26 Table 19. Programming Registers ..................................................................................................................33 Table 20. Play Master Volume Register .........................................................................................................34 Table 21. PC_BEEP Register ........................................................................................................................35 Table 22. Analog Mixer Input Gain Register ..................................................................................................36 Table 23. Record Select Control Registers ....................................................................................................37 Table 24. Record Gain Registers ..................................................................................................................38 Table 25. General Purpose Register ..............................................................................................................38 Table 26. 3D Control Registers .....................................................................................................................39 Table 27. Powerdown Status Registers .........................................................................................................40 2-9750-D1- 5.3-0604 5 STAC9750/51 Value-Line Two-Channel AC'97 Codecs with Headphone Drive and SPDIF Output Table 28. Extended Audio ID .........................................................................................................................42 Table 29. Slot assignment relationship between SPSA1 and SPSA0 ............................................................43 Table 30. STAC9750/51 AMAP compliant .....................................................................................................44 Table 31. Hardware Supported Sample Rates ...............................................................................................44 Table 32. SPDIF Control ................................................................................................................................45 Table 33. Extended Moden Status and Control .............................................................................................46 Table 34. GPIO Pin Configuration Register ...................................................................................................46 Table 36. GPIO Pin Sticky Register ...............................................................................................................47 Table 37. GPIO Pin Mask Register ................................................................................................................47 Table 35. GPIO Pin Polarity/Type Register ....................................................................................................47 Table 38. GPIO Pin Status Register ..............................................................................................................48 Table 39. Digital Audio Control Register ........................................................................................................48 Table 40. ADC data on AC LINK ....................................................................................................................50 Table 41. Mic Boost Select ............................................................................................................................50 Table 42. Analog Current Adjust ....................................................................................................................51 Table 43. GPIO Access Registers (74h) ........................................................................................................52 Table 44. Low Power Modes ..........................................................................................................................54 Table 45. Codec ID Selection ........................................................................................................................56 Table 46. Secondary Codec Register Access Slot 0 Bit Definitions ...............................................................57 Table 47. Digital Connection Signals .............................................................................................................60 Table 48. Analog Connection Signals ............................................................................................................61 Table 49. Filtering and Voltage References ...................................................................................................62 Table 50. Power and Ground Signals ............................................................................................................62 Table 51. 48-Pin TQFP Package Dimensions ................................................................................................63 6 2-9750-D1- 5.3-0604 STAC9750/51 Value-Line Two-Channel AC'97 Codecs with Headphone Drive and SPDIF Output 2. PRODUCT BRIEF 2.1. Features * * * * * * * * * * * * * * * * * Full duplex stereo 18-bit ADC and 20-bit DAC AC'97 Rev 2.2-compliant High performance technology SPDIF output Crystal elimination circuit Headphone amplifier Independent sample rates for ADC & DACs (hardware SRCs) 20 or 30dB microphone boost capability 90 dB SNR LINE-LINE 5-Wire AC-Link protocol compliance Digital-Ready architecture General purpose I/O +3.3V (STAC9751) and +5V (STAC9750) analog power supply options Pin compatible with the STAC9700/21/44/08/56/66/52 SigmaTel Surround (SS3D) Stereo Enhancement Energy saving dynamic power modes See Register Comparision Table Below CA3 3.3V Digital: 35mA 3.3V Analog: 70mA 5V Analog: 80mA SeeSection 3.1.3; page10 Uses Register 74h. Revision Comparison Item Power Supply Current CC1 3.3V Digital: 30mA 3.3V Analog: 35mA 5V Analog: 35mA SeeSection 3.1.3; page10 Uses Registers 3Eh, 4Ch, 4Eh, 50h, 52h, 54h, and 74h. Powerdown Power Consumption GPIO and EAPD Control Registers 2.2. Description SigmaTel's STAC9750/51 are general purpose 18-bit ADC, 20-bit DAC, full duplex, audio codecs conforming to the analog component specification of AC'97 (Audio Codec 97 Component Specification Rev. 2.2). The STAC9750/51 incorporate SigmaTel's proprietary technology to achieve a DAC SNR in excess of 90 dB. The DACs, ADCs, and mixer are integrated with analog I/Os, which include four analog line-level stereo inputs, two analog line-level mono inputs, two stereo outputs, and one mono output channel. The STAC9750/51 include digital input/output capability for support of modern PC systems with an output that supports the SPDIF format. The STAC9750/51 is a standard 2-channel stereo codec. With SigmaTel's headphone drive capability, headphones can be driven with no external amplifier. The STAC9750/51 may be used as a secondary codec, with the STAC9700/21/44/56/ 08/84/66 as the primary, in a multiple codec configuration conforming to the AC'97 Rev. 2.2 specification. This configuration can provide true six-channel, AC-3 play- 2-9750-D1- 5.3-0604 7 STAC9750/51 Value-Line Two-Channel AC'97 Codecs with Headphone Drive and SPDIF Output back required for DVD applications. The STAC9750/51 communicates via the five-wire AC-Link to any digital component of AC'97 providing flexibility in the audio system design. Packaged in an AC'97 compliant 48-pin TQFP, the STAC9750/51 can be placed on the motherboard, daughter boards, PCI, AMR, CNR, or ACR cards. The STAC9750/51 block diagram is illustrated in Figure 1. It provides variable sample rate Digital-to-Analog (DA) and Analog-to-Digital (AD) conversion, mixing, and analog processing. Supported audio sample rates include 48kHz, 44.1kHz, 32kHz, 22.05 kHz, 16kHz, 11.025kHz, and 8kHz; additional rates are supported in the STAC9750/51 soft audio drivers. The digital interface communicates with the AC'97 controller via the five-wire AC-Link and contains the 64-word by 16-bit registers. The two DACs convert the digital stereo PCM-out content to audio. The MIXER block combines the PCM_OUT with any analog sources, to drive the LINE_OUT and HP_OUT outputs. The MONO_OUT delivers either mic only, or a mono mix of sources from the MIXER. The stereo variable sample rate ADC's provide record capability for any mix of mono or stereo sources, and deliver a digital stereo PCM-in signal back to the AC-Link. The microphone input and mono input can be recorded simultaneously, thus allowing for an all digital output in support of the digital ready initiative. All ADC's operate at 18-bit resolution and DAC's at 20-bit resolution. For a digital ready record path, the microphone is connected to the left channel ADC while the mono output of the stereo mixer is connected to right channel ADC. Make sure the microphone input is not connected to the stereo mixer when in this mode. The STAC9750/51 supports General Purpose Input/Output (GPIO), as well as SPDIF output. These digital I/O options provide for a number of advance architectural implementations, with volume controls and digital mixing capabilities built directly into the codec. The STAC9750/51 is designed primarily to support stereo (2-speaker) audio. True AC-3 playback can be achieved for 6-speaker applications by taking advantage of the multi-codec option available in the STAC9750/51 to support multiple codecs in an AC'97 architecture. Additionally, the STAC9750/51 provides for a stereo enhancement feature, SigmaTel Surround 3D (SS3D). S S3D provides the listener with several options for improved speaker separation beyond the normal 2/ 4-speaker arrangements. Together with the logic component (controller or advanced core logic chip-set) of AC'97, STAC9750/51 can be SoundBlaster(R) and Windows Sound System(R) compatible with SigmaTel's WDM driver for WIN 98/2K/ME/XP. SoundBlaster is a registered trademark of Creative Labs. Windows is a registered trademark of Microsoft Corporation. 2.3. Ordering Information Package 48-pin TQFP 7mm x 7mm x 1.4mm 48-pin TQFP 7mm x 7mm x 1.4mm Temp Range 0 C to +70 C 0 C to +70 C Supply Range DVdd = 3.3V, AVdd = 5.0V DVdd = 3.3V, AVdd = 3.3V Part Number STAC9750T STAC9751T 8 2-9750-D1- 5.3-0604 STAC9750/51 Value-Line Two-Channel AC'97 Codecs with Headphone Drive and SPDIF Output 2.4. STAC9750/51 Block Diagram Power Management 4 stereo sources 2 mono sources Stereo Mono HP_OUT PCM out DACs AC-link SYNC BIT_CLK SDATA_OUT SDATA_IN RESET# DAC Digital Interface Registers 64x16 bits DAC MIXER ADC ADC PCM in ADCs Analog mixing and Gain Control LINE_OUT MONO_OUT Multi-Codec CID0 CID1 Mic Boost 0,20 or 30 dB M MIC1 U X MIC2 Variable Sample Rate 20-Bit DACs and 18-Bit ADCs SPDIF Figure 1. STAC9750/51 Block Diagram 2.5. Key Specifications * * * * * * Analog LINE_OUT SNR: 90 dB Digital DAC SNR: 89 dB Digital ADC SNR: 85 dB Full-scale Total Harmonic Distortion: 0.005% Crosstalk between Input Channels: -70 dB Spurious Tone Rejection: 100 dB 2.6. Related Materials * * * Product Brief Reference Designs for MB, AMR, CNR, and ACR applications Audio Precision Performance Plots 2.7. Additional Support Additional product and company information can be obtained by going to the SigmaTel website at: www.sigmatel.com 2-9750-D1- 5.3-0604 9 STAC9750/51 Value-Line Two-Channel AC'97 Codecs with Headphone Drive and SPDIF Output 3. CHARACTERISTICS/SPECIFICATIONS 3.1. Electrical Specifications 3.1.1. Absolute Maximum Ratings: Voltage on any pin relative to Ground Operating Temperature Storage Temperature Soldering Temperature Output Current per Pin Maximum Supply Voltage Vss - 0.3V TO Vdd + 0.3V 0 o C TO 70 o C -55 o C TO +125 o C 220 o C FOR 10 SECONDS 4 mA except VREFout = 5mA 5.5 Volts = Vdd 3.1.2. Power Supplies* + 3.3V Digital + 5V Analog + 3.3V Analog Ambient Temperature Recommended Operating Conditions Parameter Min 3.135 4.75 3.135 0 Typ 3.3 5 3.3 Max 3.465 5.25 3.465 70 Unit V V V o C Table 1. Recommended Operating Conditions. 3.1.3. Power Consumption . Parameter Min Typ 30 35 35 Max Unit mA mA mA Digital Supply Current + 3.3V Digital Analog Supply Current (at Reset state) + 5V Analog + 3.3V Analog Power Down Status (individually asserted) All PR measurements taken while unmuted. All paths unmuted +5V Analog Supply Current +3.3V Analog Supply Current +3.3V Digital Supply Current PR0 +5V Analog Supply Current +3.3V Analog Supply Current +3.3V Digital Supply Current - - 50 44 33 42 39 22 - mA - mA Table 2. Power Consumption The Power Consumption numbers in the table above are applicable to the STAC9750/51 CC1 revision and beyond. Revisions previous to the CC1 revision have a power consumption of 3.3V Digital: 35mA, 3.3V Analog: 70mA , and 5V Analog: 80mA. CAUTION: ESD sensitive device. Do not open or handle except at a certified static-safe work environment. The STAC9750/51 is an ESD (Electrostatic discharge) sensitive device. The human body and test equipment can accumulate and discharge without detection, electrostatic charges up to 4000 Volts. Even thought the STAC9750/51 includes ESD protection circuitry internally, proper ESD precautions should be followed to avoid damaging the functionality or performance. 10 2-9750-D1- 5.3-0604 STAC9750/51 Value-Line Two-Channel AC'97 Codecs with Headphone Drive and SPDIF Output Parameter +5V Analog Supply Current +3.3V Analog Supply Current +3.3V Digital Supply Current PR2 +5V Analog Supply Current +3.3V Analog Supply Current +3.3V Digital Supply Current PR3 +5V Analog Supply Current +3.3V Analog Supply Current +3.3V Digital Supply Current PR4 +5V Analog Supply Current +3.3V Analog Supply Current +3.3V Digital Supply Current PR5 +5V Analog Supply Current +3.3V Analog Supply Current +3.3V Digital Supply Current PR6 +5V Analog Supply Current +3.3V Analog Supply Current +3.3V Digital Supply Current PR0 & PR1 +5V Analog Supply Current +3.3V Analog Supply Current +3.3V Digital Supply Current PR0, PR1, PR2, PR6 +5V Analog Supply Current +3.3V Analog Supply Current +3.3V Digital Supply Current PR0, PR1, PR2, PR3, PR6 +5V Analog Supply Current +3.3V Analog Supply Current +3.3V Digital Supply Current PR1 Min Typ 41 38 28 32 29 12 23 19 12 50 44 0.2 50 44 12 38 36 33 35 35 12 5 5 12 0.6 0.6 12 Max Unit mA - - mA - - mA - - mA - - mA - - mA - - mA - - mA - - mA Table 2. Power Consumption (Continued) The Power Consumption numbers in the table above are applicable to the STAC9750/51 CC1 revision and beyond. Revisions previous to the CC1 revision have a power consumption of 3.3V Digital: 35mA, 3.3V Analog: 70mA , and 5V Analog: 80mA. 3.1.4. Revision Comparision CC1 % Of Savings Analog Digital Analog Digital 5V 3.3V 3.3V 5V 3.3V 3.3V 50 44 33 36% 36% -22% 42 39 22 32% 30% 4% 41 38 28 35% 27% -17% 32 29 12 33% 31% 56% 23 19 12 43% 46% 43% 50 44 0.2 34% 35% 80% 50 44 12 33% 35% -60% 38 36 33 61% 41% -22% All PR measurements taken while unmuted. No PR PR0 PR1 PR2 PR3 PR4 PR5 PR6 CA3 Analog Digital 5V 3.3V 3.3V 78 69 27 62 56 23 63 52 24 48 42 27 40 35 21 76 68 1 75 68 7.5 97 61 27 PR bit individually asserted. 2-9750-D1- 5.3-0604 11 STAC9750/51 Value-Line Two-Channel AC'97 Codecs with Headphone Drive and SPDIF Output 3.1.5. AC-Link Static Digital Specifications (Tambient = 25 C, DVdd = 3.3V 5%, AVss=DVss=0V; 50pF external load) Parameter Input Voltage Range Low level input range High level input voltage High level output voltage Low level output voltage Input Leakage Current (AC-Link inputs) Output Leakage Current (Hi-Z'd AC-Link outputs) Output buffer drive current Symbol Vin Vil Vih Voh Vol Min -0.30 0.65xDVdd 0.90xDVdd -10 -10 Typ 4 Max DVdd + 0.30 0.35xDVdd 0.1xDVdd 10 10 Unit V V V V V uA uA mA Table 3. AC-Link Static Specifications 3.1.6. STAC9750 Analog Performance Characteristics (T ambient = 25 C, AVdd = 5.0V 5%, DVdd = 3.3V 5%, AVss=DVss=0V; 1 kHz input sine wave; Sample Frequency = 48 kHz; 0 dB = 1 Vrms, 10K//50pF load, Testbench Characterization BW: 20 Hz - 20 kHz, 0 dB settings on all gain stages) Parameter Min 20 84 74 20 19,200 Typ 1.0 0.03 1.0 1.0 1.0 50 90 90 89 85 89 89 89 80 20,000 19,200 28,800 Max Unit Vrms Vrms Vrms Vrms Vrms mWpk dB dB dB dB Hz dB dB dB dB dB Hz Hz Full Scale Input Voltage: All Analog Inputs except Mic Mic Inputs (Note 1) Full Scale Output: Line Output PCM (DAC) to LINE_OUT MONO_OUT HEADPHONE_OUT (32 load) Analog S/N: (Note 2) CD to LINE_OUT Other to LINE_OUT D/A to LINE_OUT LINE_IN to A/D with High pass filter enabled Analog Frequency Response (Note 3) Total Harmonic Distortion: (Note 4) CD to LINE_OUT Other to LINE_OUT D/A to LINE_OUT (full scale) LINE_IN to A/D with High pass filter enabled HEADPHONE_OUT A/D & D/A Digital Filter Pass Band (Note 5) A/D & D/A Digital Filter Transition Band Table 4. STAC9750 Analog Performance Characteristics 12 2-9750-D1- 5.3-0604 STAC9750/51 Value-Line Two-Channel AC'97 Codecs with Headphone Drive and SPDIF Output Parameter A/D & D/A Digital Filter Stop Band A/D & D/A Digital Filter Stop Band Rejection (Note 6) DAC Out-of-Band Rejection (Note 7) Group Delay (48KHz sample rate) Any Analog Input to LINE_OUT C rosstalk (10KHz Signal Frequency) Any Analog Input to LINE_OUT Crosstalk (1KHz Signal Frequency) Spurious Tone Rejection Attenuation, Gain Step Size Input Impedance (Note 8) Input Capacitance VREFout Interchannel Gain Mismatch ADC Interchannel Gain Mismatch DAC Note: 1. 2. 3. 4. 5. 6. 7. 8. Min 28,800 100 55 70 100 100 1.5 50 15 0.5 X AVdd Typ Max 1 0.5 0.5 Unit Hz dB dB ms dB dB dB dB K pF V dB dB Table 4. STAC9750 Analog Performance Characteristics (Continued) With +30 dB Boost on, 1.0Vrms with Boost off Ratio of Full Scale signal to idle channel noise output is measured "A weighted" over a 20 Hz to a 20 kHz bandwidth. (AES17-1991 Idle Channel Noise or EIAJ CP-307 Signal-to-noise Ratio). 1dB limits for Line Output & 0 dB gain Ratio of Full Scale signal toTHD+N output with -3dB signal, measured "A weighted" over a 20 kHz BW, 48 kHz Sample Frequency 0.25dB limits Stop Band rejection determines filter requirements. Out-of-Band rejection determines audible noise. The integrated Out-of-Band noise generated by the DAC process, during normal PCM audio playback, over a bandwidth 28.8 to 100 kHz, with respect to a 1 Vrms DAC output. For all inputs except PC BEEP. 3.1.7. STAC9751 Analog Performance Characteristics (T ambient = 25 C, AVdd = DVdd = 3.3V 5%, AVss=DVss=0V; 1 kHz input sine wave; Sample Frequency = 48 kHz; 0 dB = 1 Vrms, 10K//50pF load, Testbench Characterization BW: 20 Hz - 20 kHz, 0 dB settings on all gain stages) Parameter Min Typ 1.0 0.03 0.5 0.5 0.5 12.5 90 Max Unit Vrms Vrms Vrms Vrms Vrms mWpk dB Full Scale Input Voltage: All Analog Inputs except Mic Mic Inputs (Note 1) Full Scale Output: Line Output PCM (DAC) to LINE_OUT MONO_OUT HEADPHONE_OUT (32 load) Analog S/N: (Note 2) CD to LINE_OUT Table 5. STAC9751 Analog Performance Characteristics 2-9750-D1- 5.3-0604 13 STAC9750/51 Value-Line Two-Channel AC'97 Codecs with Headphone Drive and SPDIF Output Parameter Other to LINE_OUT D/A to LINE_OUT LINE_IN to A/D with High pass filter enabled Analog Frequency Response (Note 3) Total Harmonic Distortion: (Note 4) CD to LINE_OUT Other to LINE_OUT D/A to LINE_OUT (full scale) LINE_IN to A/D with High pass filter enabled HEADPHONE_OUT A/D & D/A Digital Filter Pass Band (Note 5) A/D & D/A Digital Filter Transition Band A/D & D/A Digital Filter Stop Band A/D & D/A Digital Filter Stop Band Rejection (Note 6) DAC Out-of-Band Rejection (Note 7) Group Delay (48KHz sample rate) Any Analog Input to LINE_OUT Crosstalk (10KHz Signal Frequency) Any Analog Input to LINE_OUT Crosstalk (1KHz Signal Frequency) Spurious Tone Rejection Attenuation, Gain Step Size Input Impedance (Note 8) Input Capacitance VREFout Interchannel Gain Mismatch ADC Interchannel Gain Mismatch DAC Gain Drift Note: 1. 2. 74 20 19,200 28,800 100 55 89 89 89 84 80 70 100 100 1.5 50 15 0.5 X AVdd 100 19,200 28,800 1 0.5 0.5 dB dB dB dB dB Hz Hz Hz dB dB ms dB dB dB dB Min 20 Typ 90 89 85 Max 20,000 Unit dB dB dB Hz K pF V dB dB ppm/C 3. 4. 5. 6. 7. 8. Table 5. STAC9751 Analog Performance Characteristics (Continued) With +30 dB Boost on, 1.0Vrms with Boost off Ratio of Full Scale signal to idle channel noise output is measured "A weighted" over a 20 Hz to a 20 kHz bandwidth. (AES17-1991 Idle Channel Noise or EIAJ CP-307 Signal-to-noise Ratio).0 dB gain, 20 kHz BW, 48 kHz Sample Frequency 1 dB limits 1dB limits for Line Output & 0 dB gain Ratio of Full Scale signal toTHD+N output with -3dB signal, measured "A weighted" over a 20 kHz BW, 48 kHz Sample Frequency 0.25dB limits Stop Band rejection determines filter requirements. Out-of-Band rejection determines audible noise. The integrated Out-of-Band noise generated by the DAC process, during normal PCM audio playback, over a bandwidth 28.8 to 100 kHz, with respect to a 1 Vrms DAC output. For all inputs except PC BEEP. 14 2-9750-D1- 5.3-0604 STAC9750/51 Value-Line Two-Channel AC'97 Codecs with Headphone Drive and SPDIF Output 3.2. AC Timing Characteristics (T ambient = 25 C, AVdd = 3.3V or 5V 5%, DVdd = 3.3V 5%, AVss=DVss+0V; 50pF external load) 3.2.1. Cold Reset Trst2clk Tres_low RESET# BIT_CLK SDATA_IN Figure 2. Cold Reset Timing Parameter RESET# active low pulse width RESET# inactive to BIT_CLK startup delay Symbol Tres_low Trst2clk Min 1.0 162.8 Typ - Max - Units us ns Table 6. Cold Reset Specifications Note: BIT_CLK and SDATAIN are in a high impedance state during reset. 3.2.2. Warm Reset Tsync_high Tsync_2clk SYNC BIT_CLK Figure 3. Warm Reset Timing Parameter SYNC active high pulse width SYNC inactive to BIT_CLK startup delay Symbol Tsync_high Tsync2clk Min 1.0 162.8 Typ 1.3 Max Units us ns Table 7. Warm Reset Specifications 2-9750-D1- 5.3-0604 15 STAC9750/51 Value-Line Two-Channel AC'97 Codecs with Headphone Drive and SPDIF Output 3.2.3. Clocks Tclk_low BIT_CLK Tclk_high Tclk_period Tsync_low Tsync_high SYNC Tclk_period Figure 4. Clocks Timing Parameter BIT_CLK frequency BIT_CLK period BIT_CLK output jitter BLT_CLK high pulsewidth (Note 1) BIT_CLK low pulse width (Note 1) SYNC frequency SYNC period SYNC high pulse width SYNC low_pulse width Note: 1. Worst case duty cycle restricted to 45/55. Symbol Tclk_period Tclk_high Tclk_low Tsync_period Tsync_high Tsync_low Min 36 36 - Typ 12.288 81.4 750 40.7 40.7 48.0 20.8 1.3 19.5 Max 45 45 - Units MHz ns ps ns ns kHz us us us Table 8. Clocks Specifications The 9750/9751 supports several clock frequency inputs as described in the following table. In general, when a 24.576MHz clock xtal is not used, the xtalout pin should be tied to ground. This short to ground configures the part into an alternate clock mode and enables an on board PLL. XTL_OUT pin config xtal XTAL or open XTAL or open XTAL or open short to ground short to ground short to ground short to ground CID1 pin config float float pulldown pulldown float float pulldown pulldown CID0 pin config float pulldown float pulldown float pulldown float pulldown clock source input 24.576Mhz xtal 12.288Mhz bit clk 12.288Mhz bit clk 12.288Mhz bit clk 14.31818Mhz source1 27MHz source 48MHz source2 24.576Mhz source Codec mode P S S S P P P P codec ID 0 1 2 3 0 0 0 0 Table 9. Clock mode configuration Note:1. In the CA1 and CA2 revisions, this clock source input is 48Mhz. Note: 2. In the CA1 and CA2 revisions, this clock source input is 14.3181 MHz. 16 2-9750-D1- 5.3-0604 STAC9750/51 Value-Line Two-Channel AC'97 Codecs with Headphone Drive and SPDIF Output 3.2.4. Data Setup and Hold (47.5-75pF external load) tco BIT_CLK SDATA_OUT SDATA_IN SYNC V ih V oh V ol T setup V il Thold Figure 5. Data Setup and Hold Timing Parameter Setup to falling edge of BIT_CLK Symbol Tsetup Min 10 Typ Max Units ns ns Hold from falling edge of BIT_CLK Thold 10 Note: Setup and hold time parameters for SDATA_IN are with respect to the AC'97 controller. Table 10. Data Setup and Hold Specifications 3.2.5. Signal Rise and Fall Times (75pF external load; from 10% to 90% of Vdd) BIT_CLK Triseclk Tfallclk SDATA_IN Trisedin Tfalldin Figure 6. Signal Rise and Fall Times Timing Parameter BIT_CLK rise time BIT_CLK fall time SDATA_IN rise time SDATA_IN fall time Symbol Triseclk Tfallclk Trisedin Tfalldin Min - Typ - Max 6 6 6 6 Units ns ns ns ns Table 11. Signal Rise and Fall Times Specifications 2-9750-D1- 5.3-0604 17 STAC9750/51 Value-Line Two-Channel AC'97 Codecs with Headphone Drive and SPDIF Output 3.2.6. AC-Link Low Power Mode Timing SYNC BIT_CLK SDATA_OUT SDATA_IN Slot 1 Slot 2 Write to 0x20 Data PR4 Don't care Ts2_pdown Note: BIT_CLK not to scale Figure 7. AC-Link Low Power Mode Timing Parameter End of Slot 2 to BIT_CLK, SDATA_IN low Symbol Ts2_pdown Min - Typ - Max 1.0 Units us Table 12. AC-Link Low Power Mode Timing Specifications 3.2.7. ATE Test Mode RESET# SDATA_OUT Tsetup2rst SDATA_IN, BIT_CLK Toff Hi-Z Figure 8. ATE Test Mode Timing Parameter Setup to trailing edge of RESET# (also applies to SYNC) Rising edge of RESET# to Hi-Z delay Symbol Tsetup2rst Toff Min 15.0 - Typ - Max 25.0 Units ns ns Table 13. ATE Test Mode Specifications Note: 1. All AC-Link signals are normally low through the trailing edge of RESET#. Bringing SDATA_OUT high for the trailing edge of RESET# causes STAC9750/51 AC-Link outputs to go high impedance which is suitable for ATE in circuit testing. Once the test mode has been entered, the STAC9750/51 must be issued another RESET# with all AC-Link signals low to return to the normal operating mode. # denotes active low. 2. 3. 18 2-9750-D1- 5.3-0604 STAC9750/51 Value-Line Two-Channel AC'97 Codecs with Headphone Drive and SPDIF Output 4. TYPICAL CONNECTION DIAGRAM 2 * Ferrite Bead* *Suggested 3.3V 5% 0.1 F 1 F 0.1 F 0.1 F 10 F 0.1 F 25 AVdd1 38 AVdd2 1 DVdd1 9 DVdd2 XTL_IN 2 27 pF 12 PC_BEEP 13 PHONE SDATA_OUT 14 AUX_L 15 AUX_R 16 VIDEO_L 17 VIDEO_R 18 CD_L 19 CD_GND 20 CD_R VREF 21 MIC1 22 MIC2 23 LINE_IN_L 24 LINE_IN_R *OPTIONAL 32 0.1 F 1 F* GPIO0 LINE_OUT_L 820 pF 29 AFILT1 LINE_OUT_R MONO_OUT HP_OUT_L AVss1 26 AVss2 42 DVss1 4 DVss2 7 HP_OUT_R CAP2 GPIO1 HP_COMM NC NC NC SPDIF 31 33 34 48 40 44 43 35 36 37 39 41 VREFOUT 28 27 RESET# CID0 SDATA_IN SYNC BIT_CLK 5 6 8 10 11 45 46 47 XTL_OUT 3 24.576 MHz 27 pF 22 EMI Filter 27 pF *OPTIONAL STAC9751 CID1 EAPD *OPTIONAL 0.1 F 1 F* 820 pF 30 AFILT2 *Terminate ground plane as close to codec as possible Analog Ground Digital Ground Note: 1. 2. 3. 4. See Appendix A for specific connection requirements prior to operation. See Figure23 on page65 for split supply connections. Pin 48: To Enable SPDIF, use an 1K-10K external pulldown. To Disable SPDIF, use an 1K-10K external pullup. Do Not leave Pin 48 floating. The CD_GND signal is an AC signal return for the two CD input channels. It is normally biased at about 2.5V. The name of the pin in the AC97 specification is CD_GND, and this has confused many designers. It should not have any DC path to GND. Connecting the CD_GND signal directly to ground will change the internal bias of the entire codec, and cause bad distortion. If there is no analog CD input, then this pin can be No-Connect Figure 9. STAC 9751 Typical Connection Diagram 2-9750-D1- 5.3-0604 19 STAC9750/51 Value-Line Two-Channel AC'97 Codecs with Headphone Drive and SPDIF Output 5. AC-LINK Figure 10 shows the AC-Link point to point serial interconnect between the STAC9750/51 and its companion controller. All digital audio streams and command/status information are communicated over this AC-Link. See "Digital Interface" on page21 for details. SYNC BIT_CLK Digital DC'97 Controller SDATA_OUT SDATA_IN RESET# XTAL_OUT AC'97 Codec XTAL_IN Figure 10. AC-Link to its Companion Controller 5.1. Clocking STAC9750/51 derives its clock internally from an externally connected 24.576 MHz crystal or an oscillator through the XTAL_IN pin. Synchronization with the AC'97 controller is achieved through the BIT_CLK pin at 12.288 MHz. The beginning of all audio sample packets, or "Audio Frames", transferred over AC-Link is synchronized to the rising edge of the "SYNC" signal driven by the AC'97 controller. Data is transitioned on AC-Link on every rising edge of BIT_CLK, and subsequently sampled by the receiving side on each immediately following falling edge of BIT_CLK. 5.2. Reset There are 3 types of resets: 1. 2. 3. a "cold" reset where all STAC9750/51 logic and registers are initialized to their default state a "warm" reset where the contents of the STAC9750/51 register set are left unaltered a "register" reset which only initializes the STAC9750/51 registers to their default states After signaling a reset to the STAC9750/51, the AC'97 controller should not attempt to play or capture audio data until it has sampled a "Codec Ready" indication via register 26h from the STAC9750/51. For proper reset operation SDATA_OUT should be "0" during "cold" reset. 20 2-9750-D1- 5.3-0604 STAC9750/51 Value-Line Two-Channel AC'97 Codecs with Headphone Drive and SPDIF Output 6. DIGITAL INTERFACE 6.1. AC-Link Digital Serial Interface Protocol The STAC9750/51 communicates to the AC'97 controller via a 5-pin digital serial AC-Link interface, which is a bi-directional, fixed rate, serial PCM digital stream. All digital audio streams, commands and status information are communicated over this point-to-point serial interconnect. The AC-Link handles multiple inputs, and output audio streams, as well as control register accesses using a time division multiplexed (TDM) scheme. The AC'97 controller synchronizes all AC-Link data transaction. Table 14 shows the data streams available on the STAC9750/51: PCM Playback PCM Record data Control Status 2 output slots 2 input slots 2 output slots 2 input slots 2 Channel composite PCM output stream 2 Channel composite PCM input stream Control register write port Control register read port Table 14. STAC9750/51 Available Data Streams Synchronization of all AC-Link data transactions is handled by the AC'97 controller. The STAC9750/51 drives the serial bit clock onto AC-Link. The AC'97 controller then qualifies with a synchronization signal to construct audio frames. SYNC, fixed at 48 kHz, is derived by dividing down the serial bit clock (BIT_CLK). BIT_CLK, fixed at 12.288 MHz, provides the necessary clocking granularity to support 12, 20-bit outgoing and incoming time slots. AC-Link serial data is transitioned on each rising edge of BIT_CLK. The receiver of AC-Link data, STAC9750/51 for outgoing data and AC'97 controller for incoming data, samples each serial bit on the falling edges of BIT_CLK. The AC-Link protocol provides for a special 16-bit (13-bits defined, with 3 reserved trailing bit positions) time slot (Slot 0) wherein each bit conveys a valid tag for its corresponding time slot within the current audio frame. A "1" in a given bit position of slot 0 indicates that the corresponding time slot within the current audio frame has been assigned to a data stream, and contains valid data. If a slot is "tagged" invalid, it is the responsibility of the source of the data, (STAC9750/51 for the input stream, AC'97 controller for the output stream), to stuff all bit positions with 0's during that slot's active time. SYNC remains high for a total duration of 16 BIT_CLKs at the beginning of each audio frame. The portion of the audio frame where SYNC is high is defined as the "Tag Phase". The remainder of the audio frame where SYNC is low is defined as the "Data Phase". Additionally, for power savings, all clock, sync, and data signals may be halted by the controller. SYNC OUTGOING STREAMS INCOMING STREAMS TAG PHASE TAG CMD ADR CMD DATA PCM LEFT PCM RT NA PCM CTR PCM LSURR PCM RSURR PCM LFE PCM LALT PCM RALT RSVD TAG STATUS STATUS ADR DATA PCM LEFT PCM RT NA NA RSVD RSVD RSVD RSVD RSVD RSVD DATA PHASE Figure 11. AC'97 Standard Bi-directional Audio Frame 2-9750-D1- 5.3-0604 21 STAC9750/51 Value-Line Two-Channel AC'97 Codecs with Headphone Drive and SPDIF Output 6.1.1. AC-Link Audio Output Frame (SDATA_OUT) The audio output frame data streams correspond to the multiplexed bundles of all digital output data targeting the STAC9750/51 DAC inputs, and control registers. Each audio output frame supports up to twelve 20-bit outgoing data time slots. Slot 0 is a special reserved time slot containing 16 bits that are used for AC-Link protocol infrastructure. Within slot 0, the first bit is a global bit (SDATA_OUT slot 0, bit 15) which flags the validity for the entire audio frame. If the "Valid Frame" bit is a 1, this indicates that the current audio frame contains at least one slot time of valid data. The next 12 bit positions sampled by the STAC9750/51 indicate which of the corresponding 12 times slots contain valid data. In this way data streams of differing sample rates can be transmitted across AC-Link at its fixed 48kHz audio frame rate. The following diagram illustrates the time slot based AC-Link protocol. Data Phase Tag Phase 20.8 uS (48 kHZ) SYNC BIT_CLK SDATA_OUT 12.288 MHz valid Frame slot1 slot2 slot(12) "0" CID1 CID0 19 "0" 19 "0" 19 "0" 19 "0" End of previous audio frame Time Slot "Valid" Bits ("1" = time slot contains valid PCM data) Slot 1 Slot 2 Slot 3 Slot 12 Figure 12. AC-Link Audio Output Frame A new audio output frame begins with a low to high transition of SYNC. SYNC is synchronous to the rising edge of BIT_CLK. On the immediately following falling edge of BIT_CLK, the STAC9750/51 samples the assertion of SYNC. This following edge marks the time when both sides of AC-Link are aware of the start of a new audio frame. On the next rising edge of BIT_CLK, the AC'97 controller transitions SDATA_OUT into the first bit position of slot 0 (Valid Frame bit). Each new bit position is presented to AC-Link on a rising edge of BIT_CLK, and subsequently sampled by the STAC9750/51 o the following falling edge of BIT_CLK. This sequence n ensures that data transitions, and subsequent sample points for both incoming and outgoing data streams are time aligned. SYNC asserted first SDATA_OUT bit of frame SYNC BIT_CLK SDATA_OUT End of previous audio frame valid Frame slot1 slot2 Figure 13. Start of an Audio Output Frame SDATA_OUT's composite stream is MSB justified (MSB first) with all non-valid slots' bit positions stuffed with 0's by the AC'97 controller. When mono audio sample streams are sent from the AC'97 controller, it is necessary that BOTH left and right sample stream time slots be filled with the same data. 22 2-9750-D1- 5.3-0604 STAC9750/51 Value-Line Two-Channel AC'97 Codecs with Headphone Drive and SPDIF Output 6.1.1.1. Slot 1: Command Address Port The command port is used to control features, and monitor status (see Audio Input Frame Slots 1 and 2) of the STAC9750/51 functions including, but not limited to, mixer settings, and power management (refer to the control register section of this specification). The control interface architecture supports up to sixty-four 16-bit read/write registers, addressable on even byte boundaries. Only the even registers (00h, 02h, etc.) are valid. Odd accesses are considered invalid and return 0 0 0 0. Audio output frame slot 1 communicates control register address, and write/read command information to the STAC9750/51. Bit 19 18:12 11:0 Description Read/Write command Control Register Index Reserved Comments 1= read, 0=write sixty-four 16-bit locations, addressed on even byte boundaries Stuffed with 0's Table 15. Command Address Port Bit Assignments The first bit (MSB) sampled by STAC9750/51 indicates whether the current control transaction is a read or a write operation. The following 7 bit positions communicate the targeted control register address. The trailing 12 bit positions within the slot are reserved and must be stuffed with 0's by the AC'97 controller. 6.1.1.2. Slot 2: Command Data Port The command data port is used to deliver 16-bit control register write data in the event that the current command port operation is a write cycle (as indicated by Slot 1, bit 19). Bit Description 19:4 Control Register Write Data 3:0 Reserved Comments Stuffed with 0's if current operation is a read Stuffed with 0's Table 16. Command Data Port Bit Assignments If the current command port operation is a read then the entire slot time must be stuffed with 0's by the AC'97 controller. 6.1.1.3. Slot 3: PCM Playback Left Channel Audio output frame slot 3 is the composite digital audio left playback stream. In a typical "Games Compatible" PC this slot is composed of standard PCM (.wav) output samples digitally mixed (on the AC'97 controller or host processor) with music synthesis output samples. If a sample stream of resolution less than 20-bits is transferred, the AC'97 controller must stuff all trailing non-valid bit positions within this time slot with 0's. 6.1.1.4. Slot 4: PCM Playback Right Channel Audio output frame slot 4 is the composite digital audio right playback stream. In a typical "Games Compatible" PC this slot is composed of standard PCM (.wav) output samples digitally mixed (on the AC'97 controller or host processor) with music synthesis output samples. If a sample stream of resolution less than 20-bits is transferred, the AC'97 controller must stuff all trailing non-valid bit positions within this time slot with 0's. 2-9750-D1- 5.3-0604 23 STAC9750/51 Value-Line Two-Channel AC'97 Codecs with Headphone Drive and SPDIF Output 6.1.1.5. Slot 5: Reserved Audio output frame slot 5 is reserved for modem operation and is not used by the STAC9750/51. 6.1.1.6. Slot 6: PCM Center Channel Audio output frame slot 6 is the composite digital audio center stream used in a multi-channel application where the STAC9750/51 is programmed to accept the primary DAC PCM data from slots 6 and 9. Please refer to the register programming section for details on the multi-channel programming options. 6.1.1.7. Slot 7: PCM Left Surround Channel Audio output frame slot 7 is the composite digital audio left surround stream. In the default state, the STAC9750/51 accepts PCM data from slots 7 and 8 for the surround DACs, for output to the DAC_OUT pins. As a programming option, PCM data from slots 7 and 8 may be used to supply data to the primary DACs when slots 6 and 9 are used to drive the surround DACs. Please refer to the register programming section for details on the multi-channel programming options. 6.1.1.8. Slot 8: PCM Right Surround Channel Audio output frame slot 8 is the composite digital audio right surround stream. As a programming option, PCM data from slots 7 and 8 may be used to supply data to the primary DACs. Please refer to the register programming section for details on the multi-channel programming options. 6.1.1.9. Slot 9: PCM Low Frequency Channel Audio output frame slot 9 is the composite digital audio low frequency stream used in a multi-channel application where the STAC9750/51 is programmed to accept the primary DAC PCM data from slots 6 and 9. Please refer to the register programming section for details on the multi-channel programming options. 6.1.1.10. Slot 10: PCM Alternate Left Audio output frame slot 10 is the composite digital audio alternate left stream used in a multi-channel applications. Please refer to the register programming section for details on the multi channel programming options. 6.1.1.11. Slot 11: PCM Alternate Right Audio output frame slot 11 is the composite digital audio alternate right stream used in a multi-channel applications. Please refer to the register programming section for details on the multi channel programming options. 6.1.1.12. Slot 12: Reserved Audio output frame slot 12 is reserved for modem operations and is not used by the STAC9750/51. 24 2-9750-D1- 5.3-0604 STAC9750/51 Value-Line Two-Channel AC'97 Codecs with Headphone Drive and SPDIF Output 6.1.2. AC-Link Audio Input Frame (SDATA_IN) The audio input frame data streams correspond to the multiplexed bundles of all digital input data targeting the AC'97 controller. As is the case for audio output frame, each AC-Link audio input frame consists of 12, 20-bit time slots. Slot 0 is a special reserved time slot containing 16 bits that are used for AC-Link protocol infrastructure. Within slot 0 the first bit is a global bit (SDATA_IN slot 0, bit 15) which flags whether the STAC9750/51 i s in the "Codec Ready" state or not. If the "Codec Ready" bit is a 0, this indicates that STAC9750/51 is not ready for normal operation. This condition is normal following the de-assertion of power on reset, for example, while STAC9750/51's voltage references settle. When the AC-Link "Codec Ready" indicator bit is a 1, it indicates that the AC-Link and STAC9750/51 control/status registers are in a fully operational state. The AC'97 controller must further probe the Powerdown Control Status Register (refer to Mixer Register section) to determine exactly which subsections, if any, are ready. Prior to any attempts at putting STAC9750/51 into operation the AC'97 controller should poll the first bit in the audio input frame (SDATA_IN slot 0, bit 15) for an indication that STAC9750/51 has become "Codec Ready". Once the STAC9750/51 is sampled "Codec Ready", the next 12 bit positions sampled by the AC'97 controller indicate which of the corresponding 12 time slots are assigned to input data streams, and that they contain valid data. The following diagram illustrates the time slot based AC-Link protocol. Data Phase Tag Phase 20.8 uS (48 kHZ) SYNC BIT_CLK SDATA_IN 12.288 MHz valid Frame slot1 slot2 slot(12) "0" "0" "0" 19 "0" 19 "0" 19 "0" 19 "0" End of previous audio frame Time Slot "Valid" Bits ("1" = time slot contains valid PCM data) Slot 1 Slot 2 Slot 3 Slot 12 Figure 14. STAC9750/51 Audio Input Frame A new audio input frame begins with a low to high transition of SYNC. SYNC is synchronous to the rising edge of BIT_CLK. Immediately following the falling edge of BIT_CLK, the STAC9750/51 samples the assertion of SYNC. This falling edge marks the time when both sides of AC-Link are aware of the start of a new audio frame. On the next rising of BIT_CLK, the STAC9750/51 transitions SDATA_IN into the first bit position of slot 0 ("Codec Ready" bit). Each new bit position is presented to AC-Link on a rising edge of BIT_CLK and subsequently sampled by the AC'97 controller on the following falling edge of BIT_CLK. This sequence ensures that data transitions, and subsequent sample points for both incoming and outgoing data streams are time aligned. SDATA_IN's composite stream is MSB justified (MSB first) with all non-valid bit positions (for assigned and/or unassigned time slots) stuffed with 0's by STAC9750/ 51. SDATA_IN data is sampled on the falling edges of BIT_CLK. 2-9750-D1- 5.3-0604 25 STAC9750/51 Value-Line Two-Channel AC'97 Codecs with Headphone Drive and SPDIF Output SYNC asserted first SDATA_OUT bit of frame SYNC BIT_CLK SDATA_IN Codec Ready slot1 slot2 End of previous audio frame Figure 15. Start of an Audio Input Frame 6.1.2.1. Slot 1: Status Address Port The status port is used to monitor status for STAC9750/51 functions including, but not limited to, mixer settings, and power management. Audio input frame slot 1's stream echoes the control register index, for historical reference, for the data to be returned in slot 2. (Assuming that slots 1 and 2 had been tagged "valid" by STAC9750/51 during slot 0) Bit 19 18:12 11:2 1:0 Description Reserved Control Register Index Slot Request Reserved Stuffed with 0's Echo of register index for which data is being returned see sections below Stuffed with 0's Table 17. Status Address Port Bit Assignments Comments The first bit (MSB) generated by STAC9750/51 is always stuffed with a 0. The following 7 bit positions communicate the associated control register address, and the trailing 12 bit positions are stuffed with 0's by STAC9750/51. 6.1.2.2. Slot 2: Status Data Port The status data port delivers 16-bit control register read data. Bit 19:4 3:0 Description Control Register Read Data Reserved Comments Stuffed with 0's if tagged "invalid" Stuffed with 0's Table 18. Status Data Port Bit Assignments If Slot 2 is tagged "invalid" by STAC9750/51, then the entire slot will be stuffed with 0's. 6.1.2.3. Slot 3: PCM Record Left Channel Audio input frame slot 3 is the left channel output of STAC9750/51 input MUX, post-ADC. STAC9750/51 ADCs are implemented to support 18-bit resolution. STAC9750/51 o utputs its ADC data (MSB first), and stuffs any trailing non-valid bit positions with 0's to fill out its 20-bit time slot. 26 2-9750-D1- 5.3-0604 STAC9750/51 Value-Line Two-Channel AC'97 Codecs with Headphone Drive and SPDIF Output 6.1.2.4. Slot 4: PCM Record Right Channel Audio input frame slot 4 is the right channel output of STAC9750/51 i put MUX, n post-ADC. STAC9750/51 o utputs its ADC data (MSB first), and stuffs any trailing non-valid bit positions with 0's to fill out its 20-bit time slot. 6.1.2.5. Slot 5: Reserved Audio input frame slot 5 is reserved for modem operation and is not used by the STAC9750/51. This slot is always stuffed with 0's. 6.1.2.6. Slot 6: PCM Left Record Channel Audio input frame slot 6 is the left channel output of STAC9750/51 input MUX, post-ADC. STAC9750/51 ADCs are implemented to support 18-bit resolution. STAC9750/51 outputs its ADC data (MSB first), and stuffs any trailing non-valid bit positions with 0's to fill out its 20-bit time slot. See section 7.5.25; page49 for slot configurations and register settings. 6.1.2.7. Slot 7: PCM Left Record Channel Audio input frame slot 7 is the left channel output of STAC9750/51 input MUX, post-ADC. STAC9750/51 ADCs are implemented to support 18-bit resolution. STAC9750/51 outputs its ADC data (MSB first), and stuffs any trailing non-valid bit positions with 0's to fill out its 20-bit time slot. See section 7.5.25; page49 for slot configurations and register settings. 6.1.2.8. Slot 8: PCM Right Record Channel Audio input frame slot 8 is the right channel output of STAC9750/51 input MUX, post-ADC. STAC9750/51 ADCs are implemented to support 18-bit resolution. STAC9750/51 outputs its ADC data (MSB first), and stuffs any trailing non-valid bit positions with 0's to fill out its 20-bit time slot. See section 7.5.25; page49 for slot configurations and register settings. 6.1.2.9. Slot 9: PCM Right Record Channel Audio input frame slot 9 is the right channel output of STAC9750/51 input MUX, post-ADC. STAC9750/51 ADCs are implemented to support 18-bit resolution. STAC9750/51 outputs its ADC data (MSB first), and stuffs any trailing non-valid bit positions with 0's to fill out its 20-bit time slot. See section 7.5.25; page49 for slot configurations and register settings. 2-9750-D1- 5.3-0604 27 STAC9750/51 Value-Line Two-Channel AC'97 Codecs with Headphone Drive and SPDIF Output 6.1.2.10. Slot 10: PCM Left Record Channel Audio input frame slot 10 is the left channel output of STAC9750/51 input MUX, post-ADC. STAC9750/51 ADCs are implemented to support 18-bit resolution. STAC9750/51 outputs its ADC data (MSB first), and stuffs any trailing non-valid bit positions with 0's to fill out its 20-bit time slot. See section 7.5.25; page49 for slot configurations and register settings. 6.1.2.11. Slot 11: PCM Right Record Channel Audio input frame slot 11 is the right channel output of STAC9750/51 input MUX, post-ADC. STAC9750/51 ADCs are implemented to support 18-bit resolution. STAC9750/51 outputs its ADC data (MSB first), and stuffs any trailing non-valid bit positions with 0's to fill out its 20-bit time slot. See section 7.5.25; page49 for slot configurations and register settings. 6.1.2.12. Slot 12: Reserved Audio input frame slot 12 is reserved for modem operation and is not used by the STAC9750/51. This slot is always stuffed with 0's. 6.2. AC-Link Low Power Mode The STAC9750/51 AC-Link can be placed in the low power mode by programming register 26h to the appropriate value. Both BIT_CLK and SDATA_IN will be brought to, and held at a logic low voltage level. The AC'97 controller can wake up the STAC9750/51 by providing the appropriate reset signals. SYNC BIT_CLK SDATA_OUT SDATA_IN Note: BIT_CLK not to scale slot 2 per frame TAG Write to 0x20 DATA PR4 slot 2 per frame TAG Figure 16. STAC9750/51 Powerdown Timing BIT_CLK and SDATA_IN are transitioned low immediately (within the maximum specified time) following the decode of the write to the Powerdown Register (26h) with PR4. When the AC'97 controller driver is at the point where it is ready to program the AC-Link into its low power mode, slots (1 and 2) are assumed to be the only valid stream in the audio output frame (all sources of audio input have been neutralized). The AC'97 controller should also drive SYNC, and SDATA_OUT low after programming the STAC9750/51 to this low power mode. 28 2-9750-D1- 5.3-0604 STAC9750/51 Value-Line Two-Channel AC'97 Codecs with Headphone Drive and SPDIF Output 6.3. Waking up the AC-Link Once the STAC9750/51 has halted BIT_CLK, there are only two ways to "wake up" the AC-Link. Both methods must be activated by the AC'97 controller. The AC-Link protocol provides for a "Cold AC'97 Reset", and a "Warm AC'97 Reset". The current power down state would ultimately dictate which form of reset is appropriate. Unless a "cold" or "register" reset (a write to the Reset register) is performed, wherein the AC'97 registers are initialized to their default values, registers are required to keep state during all power down modes. Once powered down, re-activation of the AC-Link via re-assertion of the SYNC signal must not occur for a minimum of 4 audio frame times following the frame in which the power down was triggered. When AC-Link powers up it indicates readiness via the Codec Ready bit (input slot 0, bit 15). Cold Reset - a cold reset is achieved by asserting RESET# for the minimum specified time, and then bringing RESET# back HIGH. The reset occurs on the rising edge when RESET# is deasserted. By asserting and deasserting RESET#, BIT_CLK and SDATA_IN will be activated, or re-activated as the case may be, and all STAC9750/51 control registers will be initialized to their default power on reset values. Note: RESET# is an asynchronous input. (# denotes active low) Warm Reset - a warm reset will re-activate the AC-Link without altering the current STAC9750/51 register values. A warm reset is signaled by driving SYNC high for a minimum of 1us in the absence of BIT_CLK. Note: Within normal audio frames, SYNC is a synchronous input. However, in the absence of BIT_CLK, SYNC is treated as an asynchronous input used in the generation of a warm reset to the STAC9750/51. 2-9750-D1- 5.3-0604 29 STAC9750/51 Value-Line Two-Channel AC'97 Codecs with Headphone Drive and SPDIF Output 7. STAC9750/51 MIXER The STAC9750/51 includes analog and digital mixers for maximum flexibility. The analog mixer is designed to the AC'97 specification to manage the playback and record of all digital and analog audio sources in the PC environment. The analog mixer also includes several extensions of the AC'97 specification to support "all analog record" capability as well as "POP BYPASS" mode for all digital playback. The analog sources include: * * * * * * System Audio : digital PCM input and output for business, games and multimedia CD/DVD: analog CD/DVD-ROM audio with internal connections to Codec mixer Mono microphone: choice of desktop mic, with programmable boost and gain Speakerphone: use of system mic and speakers for telephone, DSVD, and video conferencing Video: TV tuner or video capture card with internal connections to Codec mixer AUX/synth: analog FM or wavetable synthesizer, or other internal source The digital mixer includes inputs for the PCM DAC and the recorded ADC output. Source PC_BEEP PHONE MIC1 MIC2 LINE_IN CD VIDEO AUX PCM out Function PC BEEP pass through to LINE_OUT MONO input desktop microphone second microphone external audio source audio from CD-ROM audio from TV tuner or video camera upgrade synth or other external source digital audio output from AC'97 Controller Connection from PC_BEEP output from telephony subsystem from mic jack from second mic jack from line-in jack cable from CD-ROM cable from TV or VidCap card internal connector AC-Link Destination HP_OUT LINE_OUT MONO_OUT PCM in SPDIF Function stereo mix of all sources stereo mix of all sources mic or MONO Analog mixer output digital data from the codec to the AC'97 Controller SPDIF digital audio output Connection To headphone out jack To output jack to telephony subsystem AC-Link To SPDIF output connector 30 2-9750-D1- 5.3-0604 STAC9750/51 Value-Line Two-Channel AC'97 Codecs with Headphone Drive and SPDIF Output KEY MonoAnalog 2Ah:D5-D4 28h: D5-D4 Slot Select 6Ah:D1 StereoAnalog PCM to SPDIF SPDIF Digital MUX PCMOut Slot Select 18h DAC PC_BEEP Phone 20h:D8 0Eh:D6 vol 0Ah 0Ch mute vol vol vol vol vol vol vol mute mute MUX mute mute mute mute mute AllAnalog vs AllRecord -6dB 04h Headphone 3D Volume 02h HP_OUT Analog Audio Sources MIC1 MIC2 LINEIN CD AUX VIDEO 20 or 30 dB 6E:D2 0Eh 10h 12h 16h 14h 20h:D15 -6dB Master Volume 06h 3D LINE_OUT MUX 6Eh:D12 1Ah MUX 20h:D9 1Ch Mono Volume MONO_OUT MUX 3D Record Volume ADC Slot Select PCMIn ADCRecord Ganged3DControl 20h:D13 22h:D2-D3 Figure 17. STAC9750 2-Channel Mixer Functional Diagram KEY MonoAnalog 2Ah:D5-D4 28h: D5-D4 Slot Select StereoAnalog 6Ah:D1 PCMOut Slot Select PCM to SPDIF SPDIF Digital MUX 18h DAC PC_BEEP Phone 20h:D8 0Eh:D6 vol -6dB 0Ah 0Ch 20 or 0Eh 10h 12h mute vol vol vol vol vol vol vol mute mute MUX mute mute mute mute mute AllAnalog vs AllRecord -6dB 04h Headphone 3D Volume 02h HP_OUT Analog Audio Sources MIC1 MIC2 -6dB 30 dB 6E:D2 20h:D15 -6dB 1Ah Master Volume 06h 3D LINE_OUT LINEIN CD -6dB MUX 6Eh:D12 MUX Mono Volume MONO_OUT AUX VIDEO -6dB -6dB -6dB -6dB 16h 14h 20h:D9 1Ch MUX 3D Record Volume +6dB ADC Slot Select PCMIn ADCRecord Ganged3DControl 20h:D13 22h:D2-D3 Figure 18. STAC9751 2-Channel Mixer Functional Diagram 2-9750-D1- 5.3-0604 31 STAC9750/51 Value-Line Two-Channel AC'97 Codecs with Headphone Drive and SPDIF Output 7.1. Analog Mixer Input The mixer provides recording and playback of any audio sources or output mix of all sources. The STAC9750/51 supports the following input sources: * * * any mono or stereo source mono or stereo mix of all sources 2-channel input w/mono output reference (mic + stereo mix) Note: All unused inputs should be tied together and have a capacitor (0.1 F suggested) to ground. 7.2. Analog Mixer Output The mixer generates three distinct outputs: * * * a stereo mix of all sources for output to the LINE_OUT and HP_OUT a stereo mix of all analog sources for recording mic only or mono mix of all sources for MONO_OUT Note:Mono output of stereo mix is attenuated by -6 dB. 7.3. SPDIF Digital Mux The STAC9750/51 incorporates a digital output that supports SPDIF formats. A multiplexer determines which of two digital input streams are used for the digital output conversion process. These two streams include the PCM OUT data from the audio controller and the ADC recorded output. The normal analog LINE_OUT signal can be converted to the SPDIF formats by using the internal ADC to record the `MIX" output, which is the combination of all analog and all digital sources. In the case of digital controllers with support for 4 or more channels, the SPDIF output mode can be used to support compressed 6-channel output streams for delivery to home theater systems. These can be routed on alternate AC-Link slots to the SPDIF output, while the standard 2-channel output is delivered as selected by bits D5 and D4 in Register 6E. If the digital controller supports 6 channels, a SPDIF output with 4 analog channels can also be configured (in a multi-codec setup). For more informa- tion for SPDIF please see 7.5.12.2; page43. Pin 48: To Enable SPDIF, use an 1K-10K external pulldown. To Disable SPDIF, use an 1K-10K external pullup. Do Not leave Pin 48 floating. 7.4. PC Beep Implementation PC Beep is active on power up and defaults to an un-muted state. The PC-BEEP input is routed directly to the MONO_OUT, LINE_OUT and HP_OUT pins of the codec. Because the PC_BEEP input drive is often a full scale digital signal, some resistive attenuation of the PC_BEEP input is recommended to keep the beep tone within reasonable volume levels. The user should mute this input before using any other mixer input because the PC Beep input can contribute noise to the lineout during normal operation. This style of PC Beep is related to the AC'97 Specification Rev 2.2. To use the analog PC Beep,a value of 00h to bits F[7:0](D[12:5]) disables the Digital PC Beep generation. PV[3:0] (D[4:1]) controls the volume level from 0 to 45dB of attenuation in 3dB steps. 32 2-9750-D1- 5.3-0604 STAC9750/51 Value-Line Two-Channel AC'97 Codecs with Headphone Drive and SPDIF Output 7.5. Address 00h 02h 04h 06h 0Ah 0Ch 0Eh 10h 12h 14h 16h 18h 1Ah 1Ch 20h 22h 24h ** 26h 28h 2Ah 2Ch 32h 3Ah 3Eh** 4Ch** 4Eh** 50h** 52h** 54h** 6Ah 6Ch 6Eh 70h 72h 74h* 76h 78h 7Ch 7Eh 1. 2. Programming Registers Name Reset Master Volume HP_OUT Mixer Volume Master Volume MONO PC Beep Mixer Volume Phone Mixer Volume Mic Mixer Volume Line In Mixer Volume CD Mixer Volume Video Mixer Volume Aux Mixer Volume PCM Out Mixer Volume Record Select Record Gain General Purpose 3D Control Audio Interrupt Powerdown Ctrl/Stat Extended Audio ID Extended Audio Control/Status PCM DAC Rate PCM LR ADC Rate SPDIF Control Extended Modem Stat/Ctl GPIO Pin Configuration GPIO Pin Polarity/Type GPIO Pin Sticky GPIO Wake-up GPIO Pin Status Digital Audio Control Revision Code Analog Special 72h Enable Analog Current Adjust GPIO Current Access 78h Enable Clock Access Vendor ID1 Vendor ID2 Default 6990h 8000h 8000h 8000h 0000h 8008h 8008h 8808h 8808h 8808h 8808h 8808h 0000h 8000h 0000h 0000h 0000h 000Fh 0205h 0400h BB80h BB80h 2A00h 0100h 0003h FFFFh 0000h 0000h 0000h 0000h 00xxh 0000h 0000h 0000h 0000h 0000h 0000h 8384h 76xxh Location 7.5.1; page34 7.5.2.1; page34 7.5.2.2; page34 and 35 7.5.2.3; page35 7.5.3; page35 7.5.4.1; page36 7.5.4.2; page36 7.5.4.3; page36 7.5.4.4; page36 7.5.4.5; page37 7.5.4.6; page37 7.5.4.7; page37 7.5.5; page37 7.5.6; page38 7.5.7; page38 7.5.8; page39 7.5.9; page39 7.5.10; page40 7.5.11; page41 7.5.12; page42 7.5.14; page44 7.5.15; page44 7.5.16; page45 7.5.17; page46 7.5.18; page46 7.5.19; page46 7.5.20; page47 7.5.21; page47 7.5.22; page48 7.5.16; page45 7.5.24; page49 7.5.25; page49 7.5.25.6; page50 7.5.25.7; page51 7.5.26; page52 7.5.27.1; page52 7.5.27.2; page53 7.5.28.1; page53 7.5.28.2; page53 Table 19. Programming Registers Register 74h is used for GPIO control in revision CA3. **Registers used in revision CC1 and beyond for GPIO. EAPD is still controled by Register 74. 2-9750-D1- 5.3-0604 33 STAC9750/51 Value-Line Two-Channel AC'97 Codecs with Headphone Drive and SPDIF Output 7.5.1. Reset (00h) Default: 6990h D15 RSRVD4 D7 ID7 D14 SE4 D6 ID6 D13 SE3 D5 ID5 D12 SE2 D4 ID4 D11 SE1 D3 ID3 D10 SE0 D2 ID2 D9 ID9 D1 ID1 D8 ID8 D0 ID0 Writing any value to this register performs a register reset, which causes all registers to revert to their default values. Reading this register returns the ID code of the part. 7.5.2. Play Master Volume Registers (Index 02h, 04h, and 06h) These registers manage the output signal volumes. Register 02h controls the stereo LINE_OUT master volume (both right and left channels), register 04h controls the Headphone Out master volume, and register 06h controls the MONO volume output. E ach step corresponds to 1.5 dB. The MSB of the register is the mute bit. When this bit is set to 1 the level for that channel is set at - dB. ML5 through ML0 is for left channel level, MR5 through MR0 is for the right channel and MM5 through MM0 is for the mono out channel. When bits D5 and D13 are set in any of these registers it automatically writes all 1's to the next lower 5-bits. The default value is 8000h for registers 02h, 04h, and 06h, which corresponds to 0 dB attenuation with mute on. Mute 0 0 1 Mx5...Mx0 00 0000 01 1111 xx xxxx Function 0dB Attenuation 46.5 Attenuation dB Attenuation Range Req. Req. Req. Table 20. Play Master Volume Register 7.5.2.1. Master Volume (02h) Default: 8000h Note: If optional bits D13, D5 of register 02h are set to 1, then the corresponding attenuation is set to 46dB and the register reads will produce 1Fh as a value for this attenuation/gain block. D15 Mute D7 D14 RSRVD D6 D13 ML5 D5 MR5 D12 ML4 D4 MR4 D11 ML3 D3 MR3 D10 ML2 D2 MR2 D9 ML1 D1 MR1 D8 ML0 D0 MR0 RESERVED 7.5.2.2. Headphone Out Volume (04h) Default: 8000h If optional bits D13, D5 of register 04h are set to 1, then the corresponding attenuation is set to 46dB and the register reads will produce 1Fh as a value for this attenuation/gain block. D15 Mute D7 D14 RSRVD D6 D13 HPL5 D5 HPR5 D12 HPL4 D4 HPR4 D11 HPL3 D3 HPR3 D10 HPL2 D2 HPR2 D9 HPL1 D1 HPR1 D8 HPL0 D0 HPR0 RESERVED 34 2-9750-D1- 5.3-0604 STAC9750/51 Value-Line Two-Channel AC'97 Codecs with Headphone Drive and SPDIF Output 7.5.2.3. Master Volume MONO (06h) Default: 8000h Note: If optional bits D5 of register 06h is set to 1, then the corresponding attenuation is set to 46dB and the register reads will produce 1Fh as a value for this attenuation/gain block. D15 Mute D7 D14 D6 D13 D5 MM5 D12 D4 MM4 D11 RESERVED D3 MM3 D10 D2 MM2 D9 D1 MM1 D8 D0 MM0 RESERVED 7.5.3. PC Beep Mixer Volume (Index 0Ah) Default: 0000h Note: PC_BEEP default to 0000h, mute off. D15 Mute D7 D14 D6 RESERVED D13 D5 D12 D4 PV3 D11 RESERVED D3 PV2 D10 D2 PV1 D9 D1 PV0 D8 D0 RSRVD This register controls the level for the PC Beep input. Each step corresponds to approximately 3 dB of attenuation. The MSB of the register is the mute bit. When this bit is set to 1, the level for that channel is set at - dB. PC_BEEP supports motherboard implementations. The intention of routing PC_BEEP through the STAC9750/51 mixer is to eliminate the requirement for an onboard speaker by guaranteeing a connection to speakers connected via the output jack. In order for this to be viable the PC_BEEP signal needs to reach the output jack at all times. NOTE: the PC_BEEP is routed to the mono outputs when the STAC9750/51 is in a RESET state. This is so that Power On Self Test (POST) codes can be heard by the user in case of a hardware problem with the PC. For further PC_BEEP implementation details please refer to the AC'97 Technical FAQ sheet. The default value is 0000h, which corresponds to 0 dB attenuation with mute off. Mute 0 0 1 PV3...PV0 0000 1111 xxxx Function 0 dB Attenuation 45 dB Attenuation dB Attenuation Table 21. PC_BEEP Register 2-9750-D1- 5.3-0604 35 STAC9750/51 Value-Line Two-Channel AC'97 Codecs with Headphone Drive and SPDIF Output 7.5.4. Analog Mixer Input Gain Registers (Index 0Ch - 18h) These registers control the gain/attenuation for each of the analog inputs. Each step corresponds to approximately 1.5 dB. The MSB of the register is the mute bit. When this bit is set to 1 the level for that channel is set at - dB. The default value for stereo registers is 8808h, corresponding to 0dB gain with mute on. Mute 0 0 0 Gx4...Gx0 00000 01000 11111 Function +12 dB gain 0 dB gain -34.5 dB gain Table 22. Analog Mixer Input Gain Register 7.5.4.1. Phone Mixer Volume (0Ch) Default: 8008h D15 Mute D7 D14 D6 RESERVED D13 D5 D12 D4 GN4 D11 RESERVED D3 GN3 D10 D2 GN2 D9 D1 GN1 D8 D0 GN0 7.5.4.2. Mic Mixer Volume (0Eh) Default: 8008h D15 Mute D7 RSRVD D6 BOOST_EN D5 RSRVD D4 GN4 D14 D13 D12 D11 RESERVED D3 GN3 D2 GN2 D1 GN1 D0 GN0 D10 D9 D8 Register 0Eh (Mic Volume Register) Bit D6 is the Mic boost enable. To select between 20db or 30db Mic Boost, see register 6Eh, D2 in section 7.5.25; page49. 7.5.4.3. Line In Mixer Volume (10h) Default: 8808h D15 Mute D7 D14 D13 RESERVED D6 RESERVED D5 D12 GL4 D4 GR4 D11 GL3 D3 GR3 D10 GL2 D2 GR2 D9 GL1 D1 GR1 D8 GL0 D0 GR0 7.5.4.4. CD Mixer Volume (12h) Default: 8808h D15 Mute D7 D14 D6 RESERVED D13 D5 D12 GL4 D4 GR4 D11 GL3 D3 GR3 D10 GL2 D2 GR2 D9 GL1 D1 GR1 D8 GL0 D0 GR0 RESERVED 36 2-9750-D1- 5.3-0604 STAC9750/51 Value-Line Two-Channel AC'97 Codecs with Headphone Drive and SPDIF Output 7.5.4.5. Video Mixer Volume (14h) Default: 8808h D15 Mute D7 D14 D6 RESERVED D13 D5 D12 GL4 D4 GR4 D11 GL3 D3 GR3 D10 GL2 D2 GR2 D9 GL1 D1 GR1 D8 GL0 D0 GR0 RESERVED 7.5.4.6. AUX Mixer Volume (16h) Default: 8808h D15 Mute D7 D14 D13 D12 GL4 D4 GR4 D11 GL3 D3 GR3 D10 GL2 D2 GR2 D9 GL1 D1 GR1 D8 GL0 D0 GR0 RESERVED D6 D5 RESERVED 7.5.4.7. PCM Out Mixer Volume (18h) Default: 8808h D15 Mute D7 D14 D13 RESERVED D6 RESERVED D5 D12 GL4 D4 GR4 D11 GL3 D3 GR3 D10 GL2 D2 GR2 D9 GL1 D1 GR1 D8 GL0 D0 GR0 7.5.5. Record Select (1Ah) Default: 0000h (corresponding to Mic in) D15 D7 D14 D6 D13 RESERVED D5 RESERVED D12 D4 D11 D3 D10 SL2 D2 SR2 D9 SL1 D1 SR1 D8 SL0 D0 SR0 Used to select the record source independently for right and left. Bit(s) 15:11 10:8 Reset 0 0 Name RESERVED SL2:SL0 Description BITS NOT USED, SHOULD READ BACK 0 LEFT CHANNEL INPUT SELECT 000 = Mic 100 = Line In (left) 001 = CD In (left) 101 = Stereo Mix (left) 010 = Video In (left) 110 = Mono Mix 011 = Aux In (left) 111 = Phone BITS NOT USED, SHOULD READ BACK 0 RIGHT CHANNEL INPUT SELECT 000 = Mic 100 = Line In (right) 001 = CD In (right) 101 = Stereo Mix (right) 010 = Video In (right) 110 = Mono Mix 011 = Aux In (right) 111 = Phone 7:3 2:0 0 0 RESERVED SR2:SR0 Table 23. Record Select Control Registers 2-9750-D1- 5.3-0604 37 STAC9750/51 Value-Line Two-Channel AC'97 Codecs with Headphone Drive and SPDIF Output 7.5.6. Record Gain (1Ch) Default: 8000h (corresponding to 0 dB gain with mute on) D15 Mute D7 D6 D14 D13 RESERVED D5 RESERVED D4 D12 D11 GL3 D3 GR3 D10 GL2 D2 GR2 D9 GL1 D1 GR1 D8 GL0 D0 GR0 The 1Ch register adjusts the stereo input record gain. Each step corresponds to 1.5 dB. 22.5 dB corresponds to 0F0Fh. The MSB of the register is the mute bit. When this bit is set to 1, the level for that channel(s) is set at - dB. Mute 0 0 1 Gx3... Gx0 1111 0000 xxxx 0 dB gain - gain Function +22.5 dB gain Table 24. Record Gain Registers 7.5.7. General Purpose (20h) Default: 0000h D15 POP BYP D7 LPBK D14 RSRVD D6 D13 3D D5 D12 D4 D11 RESERVED D3 RESERVED D10 D2 D9 MIX D1 D8 MS D0 This register is used to control some miscellaneous functions. Below is a summary of each bit and its function. The MS bit controls the mic selector. The LPBK bit enables loopback of the ADC output to the DAC input without involving the AC-Link, allowing for full system performance measurements. Bit 3D MIX MS POP BYP LPBK Function 3D Stereo Enhancement on/off 1 = on Mono output select 0 = Mix, 1= Mic Mic select 0 = Mic1, 1 = Mic2 DAC bypasses mixer and connects directly to Line Out ADC/DAC loopback mode Table 25. General Purpose Register 38 2-9750-D1- 5.3-0604 STAC9750/51 Value-Line Two-Channel AC'97 Codecs with Headphone Drive and SPDIF Output 7.5.8. 3D Control (22h) Default: 0000h D15 D7 D14 D6 D13 D12 D4 D11 D3 DP3 D10 D2 DP2 D9 D8 RESERVED D5 RESERVED D1 D0 RESERVED This register is used to control the 3D stereo enhancement function, Sigmatel Surround 3D (SS3D), built into the AC'97 component. Note that register bits DP3-DP2 are used to control the separation ratios in the 3D control for LINE_OUT. SS3D provides for a wider soundstage extending beyond the normal 2-speaker arrangement. Note that the 3D bit in the general purpose register (20h) must be set to 1 to enable SS3D functionality and for the bits in 22h to take effect. DP3, DP2 00 01 10 11 LINE_OUT SEPARATION RATIO 0 (Off) 3 (Low) 4.5 (Med) 6 (High) Table 26. 3D Control Registers The three separation ratios are implemented as shown in Table 26. The separation ratio defines a series of equations that determine the amount of depth difference (High, Medium, and Low) perceived during two-channel playback. The ratios provide for options to narrow or widen the soundstage. 7.5.9. Audio Interrupt (24h) For use with Revsion CC1 GPIO interrupts. Default: 0000h D15 I4 D7 D14 I3 D6 D13 D12 D11 I0 D3 D10 D2 D9 RESERVED D1 D8 D0 RESERVED D5 D4 RESERVED Bit(s) Reset R/W Value 15 0 RW Name I4 Description 0=Interrupt is clear 1=interrupt is set Interrupt event is cleared by writing a "1" to this bit. The interrupt bit will change regardless of condition of interrupt enable (I0) status. An interrupt in the GPI in slot 12 in the ACLink will follow this bit change when interrupt enable (I0) is unmasked. Interrupt Cause 0 = No Interrupt Caused 1 = Change in GPIO input status These bits will reflect the general cause of the first interrupt event generated. It should be read after interrupt status has been confirmed as interrupting. The information should be used to scan possible interrupting events in proper pages . 14 0 RO I3 2-9750-D1- 5.3-0604 39 STAC9750/51 Value-Line Two-Channel AC'97 Codecs with Headphone Drive and SPDIF Output Bit(s) Reset R/W Value 13-12 11 0 0 Name Description RW RESERVED BITS NOT USED, SHOULD READ BACK 0 RW I0 Interrupt Enable 0 = Interrupt generation is masked. 1 = Interrupt generation is un-masked. The driver should not un-mask the interrupt unless ensured by the AC `97 controller that no conflict is possible with modem slot 12 - GPI functionality. Some AC'97 2.2 compliant controllers will not likely support audio codec interrupt infrastructure. In either case, S/W should poll the interrupt status after initiating a sense cycle and wait for Sense Cycle Max Delay to determine if an interrupting event has occurred. 10:0 0 RO RESERVED BITS NOT USED, SHOULD READ BACK 0 7.5.10. Powerdown Ctrl/Stat (26h) Default: 000Fh D15 EAPD D7 D14 PR6 D6 D13 PR5 D5 D12 PR4 D4 D11 PR3 D3 REF D10 PR2 D2 ANL D9 PR1 D1 DAC D8 PR0 D0 ADC RESERVED This read/write register is used to program powerdown states and monitor subsystem readiness. The EAPD external control is also supported through this register. Bit EAPD REF ANL DAC ADC Function External Amplifier Power Down VREF's up to nominal level Analog mixers, etc. ready DAC section ready to playback data ADC section ready to playback data Table 27. Powerdown Status Registers 7.5.10.1. Ready Status The lower half of this register is read only status, a "1" indicating that the subsection is "ready". Ready is defined as the subsection's ability to perform in its nominal state. When this register is written, the bit values that come in on AC-Link will have no effect on read only bits 0-7. When the AC-Link "Codec Ready" indicator bit (SDATA_IN slot 0, bit 15) is a 1, it indicates that the AC-Link and AC'97 control and status registers are in a fully operational state. The AC'97 controller must further probe this Powerdown Control/Status Register to determine exactly which subsections, if any are ready. When this register is written, the bit values that come in on AC-Link will have no effect on read only bits 0-7. 40 2-9750-D1- 5.3-0604 STAC9750/51 Value-Line Two-Channel AC'97 Codecs with Headphone Drive and SPDIF Output 7.5.10.2. Powerdown Controls The STAC9750/51 is capable of operating at reduced power when no activity is required. The state of power down is controlled by the Powerdown Register (26h). See the section "Low Power Modes" for more information. 7.5.10.3. External Amplifier Power Down Control The EAPD bit 15 of the Powerdown Control/Status Register (Index 26h) directly controls the output of the EAPD output, pin 45, and produces a logical "1" when this bit is set to logic high. This function is used to control an external audio amplifier power down. EAPD = 0 places approximately 0V on the output pin, enabling an external audio amplifier. EAPD = 1 places approximately DVdd on the output pin, disabling the external audio amplifier. Audio amplifiers that operate with reverse polarity will likely require an external inverter to maintain software driver compatibility. 7.5.11. D15 ID1 D7 SDAC D14 ID0 D6 CDAC Extended Audio ID (28h) Default: 0605h D13 D5 DSA1 D12 D4 DSA0 D11 REV1 D3 VRM D10 REV0 D2 SPDIF D9 AMAP D1 DRA D8 LDAC D0 VRA RESERVED The Extended Audio ID register is a read only register, except for Bits D5:D4. ID1 and ID0 echo the configuration of the codec as defined by the programming of pins 45 and 46 externally. "00" returned defines the codec as the primary codec, while any other code identifies the codec as one of three secondary codec possibilities. SDAC=0 tells the controller that the STAC9750/51 is a two-channel codec as defined by the Intel spec. The AMAP bit, D9, will return a 1 indicating that the codec supports the optional "AC'97 2.2 compliant AC-link slot to audio DAC mappings". The default condition assumes that 0, 0 are loaded in the DSA0 and DSA1 bits of the Extended Audio ID (Index 28h). With 0s in the DSAx bits, the codec slot assignments are as per the AC'97 specification recommendations. If the DSAx bits do not contain 0s, the slot assignments are as per the table in the section describing the Extended Audio ID (Index 28h). The VRA bit, D0, will return a 1 indicating that the codec supports the optional variable sample rate conversion as defined by the AC'97 specification. 2-9750-D1- 5.3-0604 41 STAC9750/51 Value-Line Two-Channel AC'97 Codecs with Headphone Drive and SPDIF Output Bit 15:14 Name ID [1,0] Access Read only 13:12 Reserved Read only 11:10 9 8 7 6 5:4 Rev[1:0] Read only AMAP LDAC SDAC CDAC Read only Read only Read only Read only Reset Value Function variable 0,0=XTAL_OUT grounded (note 1) CID1#,CID0#=XTAL_OUT crystal or floating 00 Reserved 01 1 0 0 0 00 Indicates codec is AC'97 Rev 2.2 compliant Multi-channel slot support (Always = 1) Low Frequency Effect, not supported (Always=0) Surround DAC, not supported (Always = 0) Center channel, not supported (Always = 0) DAC slot assignment If CID[1:0]=00 then DSA[1:0] resets to 00 If CID[1:0]=01 then DSA[1:0] resets to 01 If CID[1:0]=10 then DSA[1:0] resets to 01 If CID[1:0]=11 then DSA[1:0] resets to 10 00 = left slot 3, right slot 4 01 = left slot 7, right slot 8 10 = left slot 6, right slot 9 11 = left slot 10, right slot 11 Variable Sample Rate Mic, not supported (Always = 0) 0=SPDIF pulled high on reset, SPDIF disabled 1=default, SPDIF enabled (Note 2) Double Rate Audio,not supported (always = 0) Variable sample rates supported (Always = 1) DSA [1,0] Read/Write 3 2 1 0 1. VRM SPDIF DRA VRA Read only Read only Read only Read only 0 1 0 1 2. Table 28. Extended Audio ID External CID pin status (from analog) these bits are the logical inversion of the pin polarity (pin 45-46). These bits are zero if XTAL_OUT is grounded with an alternate external clock source in primary mode only. Secondary mode can either be through BIT CLK driven or 24MHz clock driver with XTAL_OUT floating/shorted. If pin 48 is held high at powerup, this bit will be held to zero, to indicate the SPDIF is not available. Pin 48: To Enable SPDIF, use an 1K-10K external pulldown. To Disable SPDIF, use an 1K-10K external pullup. Do Not leave Pin 48 floating. 7.5.12. Extended Audio Control/Status (2Ah) Default: 0400h D15 D14 D13 RESERVED D5 SPSA1 D12 D4 SPSA0 D11 D3 RSRVD D10 SPCV D2 SPDIF D9 D1 RSRVD D8 D0 VRA enable RESERVED D7 D6 RESERVED 7.5.12.1. Variable Rate Sampling Enable The Extended Audio Status Control register also contains one active bit to enable or disable the Variable Sampling Rate capabilities of the DACs and ADCs. If the VRA, bit D0, is 1 the variable sample rate control registers (2Ch and 32h) are active, and 42 2-9750-D1- 5.3-0604 STAC9750/51 Value-Line Two-Channel AC'97 Codecs with Headphone Drive and SPDIF Output "on-demand" slot data required transfers are allowed. If the VRA bit is 0, the DACs and ADCs will operate at the default 48 kHz data rate. The STAC9750/51 supports "on-demand" slot request flags. These flags are passed from the codec to the AC'97 controller in every audio input frame. Each time a slot request flag is set (active low) in a given audio frame, the controller will pass the next PCM sample for the corresponding slot in the audio frame that immediately follows. The VRA enable bit must be set to 1 to enable "on-demand" data transfers. If the VRA enable bit is not set, the codec will default to 48 kHz transfers and every audio frame will include an active slot request flag and data is transferred every frame. For variable sample rate output, the codec examines its sample rate control registers, the state of the FIFOs, and the incoming SDATA_OUT tag bits at the beginning of each audio output frame to determine which SLOTREQ bits to set active (low). SLOTREQ bits are asserted during the current audio input frame for active output slots, which will require data in the next audio output frame. For variable sample rate input, the tag bit for each input slot indicates whether valid data is present or not. Thus, even in variable sample rate mode, the codec is always the master: for SDATA_IN (codec to controller), the codec sets the TAG bit; for SDATA_OUT (controller to codec), the codec sets the SLOTREQ bit and then checks for the TAG bit in the next frame. Whenever VRA is set to 0 the PCM rate registers (2Ch and 32h) are overwritten with BB80h (48 kHz). 7.5.12.2. SPDIF The SPDIF bit in the Extended Audio Status Control Register is used to enable and disable the SPDIF functionality within the STAC9750/51. If the SPDIF is set to a 1, then the function is enabled and when set to a 0 it is disabled. 7.5.12.3. SPCV (SPDIF Configuration Valid) The SPCV bit is read only and indicates whether or not the SPDIF system is set up correctly. When SPCV is a 0, it indicates the system configuration is invalid and valid if it is a 1. 7.5.12.4. SPSA1, SPSA0 (SPDIF Slot Assignment) SPSA1 and SPSA0 combine to provide the slot assignments for the SPDIF data. The following details the slot assignment relationship between SPSA1 and SPSA0. SPSA[1,0] 00 01 10 11 Slot Assignment 3&4 7&8 6&9 10 & 11 Comments SPDIF source data slot assignment 2-ch codec primary default 4-ch codec primary default 6-ch codec primary default Table 29. Slot assignment relationship between SPSA1 and SPSA0 2-9750-D1- 5.3-0604 43 STAC9750/51 Value-Line Two-Channel AC'97 Codecs with Headphone Drive and SPDIF Output The STAC9750/51 are AMAP compliant with the following table. Codec ID 00 01 Function 2-ch Primary w/SPDIF 2-ch Dock Codec w/SPDIF SPSA = 00 SPSA = 01 SPSA = 10 SPSA = 11 3&4 3&4 3&4 3&4 7 & 8* 7&8 7&8 7&8 6&9 6 & 9* 6 & 9* 6&9 10 & 11 10 & 11 10 & 11 10 & 11* 10 +2-ch Surr w/ SPDIF 11 +2-ch Cntr/LFE w/ SPDIF Note:* is the default slot assignment Table 30. STAC9750/51 AMAP compliant 7.5.13. PCM DAC Rate Registers (2Ch and 32h) The internal sample rate for the DACs and ADCs are controlled by the value in these read/write registers that contain a 16-bit unsigned value between 0 and 65535 representing the conversion rate in Hz. In VRA mode (register 2Ah bit D0 = 1), if the value written to these registers is supported that value will be echoed back when read, otherwise the closest (higher in the case of a tie) sample rate is supported and returned. P er PC 99 / PC 2001 specification, independent sample rates are supported for record and playback. Whenever VRA is set to 0 the PCM rate registers (2Ch and 32h) will readback with BB80h (48 kHz). Sample Rate 8 kHz 11.025 kHz 16 kHz 22.05 kHz 32 kHz 44.1 kHz 48 kHz SR15-SR0 Value 1F40h 2B11h 3E80h 5622h 7D00h AC44h BB80h Table 31. Hardware Supported Sample Rates 7.5.14. PCM DAC Rate (2Ch) Default: BB80h D15 SR15 D7 SR7 D14 SR14 D6 SR6 D13 SR13 D5 SR5 D12 SR12 D4 SR4 D11 SR11 D3 SR3 D10 SR10 D2 SR2 D9 SR9 D1 SR1 D8 SR8 D0 SR0 7.5.15. PCM LR ADC Rate (32h) Default: BB80h D15 SR15 D7 SR7 D14 SR14 D6 SR6 D13 SR13 D5 SR5 D12 SR12 D4 SR4 D11 SR11 D3 SR3 D10 SR10 D2 SR2 D9 SR9 D1 SR1 D8 SR8 D0 SR0 44 2-9750-D1- 5.3-0604 STAC9750/51 Value-Line Two-Channel AC'97 Codecs with Headphone Drive and SPDIF Output 7.5.16. SPDIF Control (3Ah) Default: 2A00h D15 #V D7 CC3 D14 DRS D6 CC2 D13 SPSR1 D5 CC1 D12 SPSR2 D4 CC0 D11 L D3 PRE D10 CC6 D2 COPY D9 CC5 D1 #PCM/AUDIO D8 CC4 D0 PRO Register 3Ah is a read/write register that controls SPDIF functionality and manages bit fields propagated as channel status (or sub-frame in the V case). With exception of V, this register should only be written to when the SPDIF transmitter is disabled (SPDIF bit register 2 Ah is "0"). This ensures that control and status information start up correctly at the beginning of SPDIF transmission. The default is 2A00h which sets the SPDIF output sample rate at 48kHz and the normal SPDIF expectations. Bit(s) Reset 15 0 Access Read & Write Name #V Description (note 1-2) Validity bit is set indicating each sub-frame's samples are invalid. If #V is 0, then it indicates that each sub-frame was transmitted and received correctly by the interface. 1 = Double Rate SPDIF support (always = 0) 14 13:12 0 10 Read Only DRS 11 0 10:4 3 2 1 0 0 0 0 0 0 Read & Write SPSR[1,0] SPDIF Sample Rate. 00 44.1 kHz Rate 01 Reserved 10 48 kHz Rate (default) 11 32 kHz Rate Read & Write L Generation Level is defined by the IEC standard, or as appropriate. (Always = 1) Read & Write CC[6, 0] Category Code is defined by the IEC standard or as appropriate by media. Read & Write PRE 0 = 0 usec Pre-emphasis 1 = Pre-emphasis is 50/15 usec Read & Write COPY 0 = Copyright not asserted 1 = Copyright is asserted Read & Write /AUDIO 0 = PCM data 1 = Non-Audio or non-PCM format Read & Write PRO 0 = Consumer use of the channel 1 = Professional use of the channel Table 32. SPDIF Control 1. 2. If pin 48 is held high at powerup, 28h D2 will be low indicating no SPDIF available and the register 3Ah will then read back 0000h. Pin 48: To Enable SPDIF, use an 1K-10K external pulldown. To Disable SPDIF, use an 1K-10K external pullup. Do Not leave Pin 48 floating. Bits D15,D13-D00 of this register cannot be written to without first setting Reg 2Ah bit D2=0 (SPDIF disabled) and Register 28h bit D2=1 (SPDIF avaliable). 2-9750-D1- 5.3-0604 45 STAC9750/51 Value-Line Two-Channel AC'97 Codecs with Headphone Drive and SPDIF Output 7.5.17. Extended Modem Status and Control Register (3Eh) (Used in Revision CC1 and beyond) Default: 0100h D15 D7 D14 D6 D13 D5 D12 RESERVED D4 RESERVED Bit(s) 15:9 8 7:1 0 Access Read Only Read / Write Read Only Read Only Reset Value 0 1 0 0 Name RESERVED PRA RESERVED GPIO Description BIT NOT USED, SHOULD READ BACK 0 0=GPIO powered up / enabled 1=GPIO powered down / disabled BIT NOT USED, SHOULD READ BACK 0 0 = GPIO not ready (powered down) 1 = GPIO ready (powered up) D11 D3 D10 D2 D9 D1 D8 PRA D0 GPIO Table 33. Extended Moden Status and Control 7.5.18. GPIO Pin Configuration Register (4Ch) (Used in Revision CC1 and beyond) Default: 0003h D13 D5 D12 D11 RESERVED D4 D3 D10 D2 D9 D1 GC1 (GPIO1) Description BIT NOT USED, SHOULD READ BACK 0 0 = GPIO1 configured as output 1 = GPIO1 configured as input 0 = GPIO0 configured as output 1 = GPIO0 configured as input D8 D0 GC0 (GPIO0) D15 D7 D14 D6 RESERVED Bit(s) 15:2 1 0 Access Read Only Read / Write Read / Write Reset Value 0 1 1 Name RESERVED GC1 GC0 Table 34. GPIO Pin Configuration Register 7.5.19. GPIO Pin Polarity/Type Register (4Eh)(Used in Revision CC1 and beyond) Default: FFFFh D15 D7 D14 D6 D13 D5 D12 D11 D10 D2 D9 D1 GP1 (GPIO1) D8 D0 GP0 (GPIO0) RESERVED D4 D3 RESERVED 46 2-9750-D1- 5.3-0604 STAC9750/51 Value-Line Two-Channel AC'97 Codecs with Headphone Drive and SPDIF Output Bit(s) 15:2 1 Access Read Only Read / Write Reset Value 0 1 Name RESERVED GP1 Description BIT NOT USED, SHOULD READ BACK 0 0 = GPIO1 Input Polarity Inverted, CMOS output drive. 1 = GPIO1 Input Polarity Non-inverted, Open-Drain output drive. 0 = GPIO0 Input Polarity Inverted, CMOS output drive. 1 = GPIO0 Input Polarity Non-inverted, Open-Drain output drive. 0 Read / Write 1 GP0 Table 35. GPIO Pin Polarity/Type Register 7.5.20. GPIO Pin Sticky Register (50h) (Used in Revision CC1 and beyond) Default: 0000h D15 D7 D14 D6 D13 D5 D12 D11 RESERVED D4 D3 D10 D2 D9 D1 GS1 (GPIO1) D8 D0 GS0 (GPIO0) RESERVED Bit(s) 15:2 1 0 Access Read Only Read / Write Read / Write Reset Value 0 0 0 Name RESERVED GS1 GS0 Description BIT NOT USED, SHOULD READ BACK 0 0 = GPIO1 Non Sticky configuration. 1 = GPIO1 Sticky configuration. 0 = GPIO0 Non Sticky configuration. 1 = GPIO0 Sticky configuration. Table 36. GPIO Pin Sticky Register 7.5.21. GPIO Pin Mask Register (52h)(Used in Revision CC1 and beyond) Default: 0000h D15 D7 D14 D6 D13 D5 D12 D11 RESERVED D4 D3 D10 D2 D9 D1 GW1 (GPIO1) D8 D0 GW0 (GPIO0) RESERVED Bit(s) 15:2 1 0 Access Read Only Read / Write Read / Write Reset Value 0 0 0 Name RESERVED GW1 GW0 Description BIT NOT USED, SHOULD READ BACK 0 0 = GPIO1 interrupt not passed to GPIO_INT slot 12. 1 = GPIO1 interrupt is passed to GPIO_INT slot 12. 0 = GPIO0 interrupt not passed to GPIO_INT slot 12. 1 = GPIO0 interrupt is passed to GPIO_INT slot 12. Table 37. GPIO Pin Mask Register 2-9750-D1- 5.3-0604 47 STAC9750/51 Value-Line Two-Channel AC'97 Codecs with Headphone Drive and SPDIF Output 7.5.22. GPIO Pin Status Register (54h) (Used in Revision CC1 and beyond) Default: 0000h D15 D7 D14 D6 D13 D12 D11 D3 D10 D2 D9 D1 GI1 (GPIO1) D8 D0 GI0 (GPIO0) RESERVED D5 D4 RESERVED Bit(s) 15:2 1 Access Read Only Read / Write Reset Value 0 x Name GI1 Description When GPIO1 is configured as output and Register h74 bit[0] = 0 (default), the value of this register will be placed on the GPIO1 pad. When GPIO1 is configured as output and Register h74 bit[0] =1, the GPIO1 pad will get its value from slot12. When GPIO1 is configured as input and configured as a sticky writing a 1 does nothing, writing a 0 clears this bit. When GPIO1 is configured as input this register reflects the value on the GPIO1 pad after interpretation of the polarity and sticky configurations. RESERVED BIT NOT USED, SHOULD READ BACK 0 0 Read / Write x GI0 When GPIO0 is configured as output and Register h74 bit[0] = 0 (default), the value of this register will be placed on the GPIO0 pad. When GPIO0 is configured as output and Register h74 bit[0] =1, the GPIO0 pad will get its value from slot12. When GPIO0 is configured as input and configured as a sticky writing a 1 does nothing, writing a 0 clears this bit. When GPIO0 is configured as input this register reflects the value on the GPIO0 pad after interpretation of the polarity and sticky configurations. Table 38. GPIO Pin Status Register 7.5.23. Digital Audio Control (6Ah) Default: 0000h D15 D7 D14 D6 D13 D5 D12 D11 RESERVED D4 D3 D10 D2 D9 D1 DO1 Description D8 D0 DO0 RESERVED Bit(s) 15:2 1 Reset 0 0 Name RESERVED DO1 0 0 DO0 BITS NOT USED, SHOULD READ BACK 0 SPDIF Digital Output Source Selection: DO1 = 0; PCM data from the AC-Link to SPDIF DO1 = 1; ADC record data to SPDIF Always reads zero Table 39. Digital Audio Control Register 48 2-9750-D1- 5.3-0604 STAC9750/51 Value-Line Two-Channel AC'97 Codecs with Headphone Drive and SPDIF Output This read/write register is used to program the digital mixer input status. In the default state, the PCM DAC path is enabled and the ADC record inputs are disabled. The DO1 and DO0 bits control the input source for the PCM to digital output converters. The table describes the available options. 7.5.24. Revision Code (6Ch) Default: 00xxh D15 0 D7 0 D14 0 D6 0 D13 0 D5 0 D12 0 D4 0 D11 0 D3 0 D10 0 D2 0 D9 0 D1 0 D8 0 D0 0 The device Revision register (index 6Ch) contains a software readable revision-specific code used to identify performance, architectural, or software differences between various device revisions. Bits 7:0 of the Revision register are user readable; bits 15:8 are not used at this time and will return zeros when read. This value can be used by the audio driver, or miniport driver in the case of WIN98(R) WDM approaches, to adjust software functionality to match the feature-set of the STAC9750/51. This will allow the software driver to identify any required operational differences between the existing STAC9750/51 and any future versions. 7.5.25. Analog Special (6Eh) Default: 0000h D15 D7 RSVD D14 RESERVED D6 MUTE FIX DISABLE D13 D5 D12 AC97 ALL MIX D4 ADCSLT0 D11 D3 RESERVED D10 D2 D9 D8 D0 SPLYOVR VAL RESERVED D1 SPLYOVR EN ADCSLT1 20/30 SEL The Analog Special Register has several bits used to control various functions specific to the STAC9750/51. 7.5.25.1. ALL MIX The AC'97 ALL MIX, bit D12 of register 6Eh, controls the record source when the Stereo Mix option is selected for recording. If the AC97 mode is default logic 1, the Stereo Mix Record option will include the sum of the analog sources with or without 3D enhancement, and the main PCM DAC output. If the "ALL Analog Record" option is selected, the Stereo Mix Record option will include the sum of the analog sources only, with or without 3D enhancement. The "AC'97 mode" is useful for recording all sound sources. The "ALL Analog" mode is useful in conjunction with the POP BYPASS mode for recording all analog sources, which are often further processed and combined with other PCM data to be output directly to the DAC outputs which are configured in POP_BYPASS mode using the General Purpose register (index 20h). 2-9750-D1- 5.3-0604 49 STAC9750/51 Value-Line Two-Channel AC'97 Codecs with Headphone Drive and SPDIF Output 7.5.25.2. ADC Data on AC LINK Bits D5-D4 select slots for ADC data on ACLINK. Value 00 01 10 11 Function left slot 3, right slot 4 left slot 7, right slot 8 left slot 6, right slot 9 left slot 10, right slot 11 Table 40. ADC data on AC LINK 7.5.25.3. MuteFix Disable (Used in Revision CC1 and beyond) Bit D6 controls the enable and disable of the MuteFix functions. 0 = MUTE FIX Enabled 1 = MUTE FIX Disabled When this bit is zero, and either channel is set to -46.5dB attenuation, 1Fh, then that channel is fully muted. When this bit is one, then operation is per AC'97 specificaiton. This bit is RESERVED in revisions prior to CC1. 7.5.25.4. Mic Boost Select The Mic boost value can be selected with Bit D2, which in enabled by Register 0Eh, bit D6. Writing a zero to Bit 2 will provide 20dB of Mic Boost. Writing a one will provide 30dB of Mic Boost. Value 0 1 Table 41. Mic Boost Select Function 20dB 30dB 7.5.25.5. Supply Override Select The Supply Override bit, D1, allows override of the supply detect. Writing a zero disables the override on supply detect. Writing a one, overrides supply detect with Bit D0. Bit D0 provides the supply override value. A zero forces 3.3V analog operation and one forces 5V analog operation. 7.5.25.6. 72h Enable (70h) Default: 0000h D15 EN15 D7 EN7 D14 EN14 D6 EN6 D13 EN13 D5 EN5 D12 EN12 D4 EN4 D11 EN11 D3 EN3 D10 EN10 D2 EN2 D9 EN9 D1 EN1 D8 EN8 D0 EN0 50 2-9750-D1- 5.3-0604 STAC9750/51 Value-Line Two-Channel AC'97 Codecs with Headphone Drive and SPDIF Output 7.5.25.7. Analog Current Adjust (72h) Default: 0000h D15 D7 INT APOP D14 D6 D13 D12 D11 D3 D10 D2 IBIAS1 D9 D1 IBIAS0 D8 D0 RSVD RESERVED D5 D4 RESERVED The Analog Current Adjust register (index 72h) is a locked register and can only be properly written and read from when ABBAh has been written into register 70h. The BIASx bits allow the analog current to be adjusted with minimal reduction in performance. A lower analog current setting is NOT recommended when a 5V analog supply is used. A lower setting for 3.3V supplies is recommended to reduce power consumption for notebook computers to its lowest level. IBIAS1 0 0 1 1 IBIAS0 0 1 0 1 Analog Current Normal Current 80% of nominal Analog Current 120% of nominal Analog Current 140% of nominal Analog Current Table 42. Analog Current Adjust 7.5.25.8. Internal Power-On/Off Anti-Pop Circuit The STAC9750/51 includes an internal power supply anti-pop circuit that prevents audible clicks and pops from being heard when the codec is powered on and off. This function is accomplished by delaying the charge/discharge of the VREF capacitor (Pin 27). CVREF value of 1uF will cause a turn-on delay of roughly 3 seconds, which will allow the power supplies to stabilize before the codec outputs are enabled. The delay will be extended to 30 seconds if a value of CVREF value of 10uF is used. The codec outputs are also kept stable for the same amount of time at power-off to allow the system to be gracefully turned off. The INT_APOP bit D7 of register 72h allows this delay circuit to be bypassed for rapid production testing. Any external component anti-pop circuit is unaffected by the internal circuit. 2-9750-D1- 5.3-0604 51 STAC9750/51 Value-Line Two-Channel AC'97 Codecs with Headphone Drive and SPDIF Output 7.5.26. GPIO Access Register (74h) (Used only in CA3 revision for GPIO) EAPD Access for ALL revisions is Register 74h. Default: 0800h D15 EAPD D7 D14 RESERVED D6 D13 GPIO1 D5 D12 GPIO0 D4 D11 D10 D9 D8 EAPD_OEN RESERVED GPIO1_OEN GPIO0_OEN D3 D2 D1 D0 RESERVED Bit(s) 15 14 13 12 11 10 9 8 7:0 Reset Value 0 0 0 0 1 0 0 0 0 Name EAPD RESERVED GPIO1 GPIO0 EAPD_OEN RESERVED GPIO1_OEN GPIO0_OEN RESERVED Description EAPD data output on EAPD when bit D11=1 EAPD data input from pin when bit D11=0 RESERVED GPIO1 data output on GPIO1 when bit D9=1 GPIO1 data input from pin when bit D9=0 GPIO0 data output on GPIO0 when bit D8=1 GPIO0 data input from pin when bit D8=0 0 = EAPD data out disabled 1 = EAPD data output enabled RESERVED 0 = GPIO1 data out disabled 1 = GPIO1 data output enabled 0 = GPIO0 data out disabled 1 = GPIO0 data output enabled RESERVED Table 43. GPIO Access Registers (74h) The GPIO Access Register requires the output enable bits (D11, D9 and D8) be used in conjunction with the data source selection (input or output) for the EAPD, GPIO0 and GPIO1 (pins 47, 43 and 44 respectively) . For example, to use GPIO1 as an output, set D9=1 to enable the output, and use D13 to write the output value desired. To use GPIO1 as an input, set D9=0 to disable the output, and use D13 to read the input value. 7.5.27. High Pass Filter Bypass (Index 76h and 78h) The High Pass Filter Bypass register (index 78h) is a locked register and can only be properly written and read from when ABBAh has been written into register 76h. Bit D0 controls the High Pass Filter Bypass. Default is zero which provides for normal operation where the high pass filter is active. Writing a one, will disable, or bypass the ADC high pass filter. 7.5.27.1. 78h Enable (76h) Default: 0000h D15 EN15 D7 EN7 D14 EN14 D6 EN6 D13 EN13 D5 EN5 D12 EN12 D4 EN4 D11 EN11 D3 EN3 D10 EN10 D2 EN2 D9 EN9 D1 EN1 D8 EN8 D0 EN0 52 2-9750-D1- 5.3-0604 STAC9750/51 Value-Line Two-Channel AC'97 Codecs with Headphone Drive and SPDIF Output 7.5.27.2. ADC High Pass FIlter Bypass(78h) Default: 0000h D15 D7 D14 D6 D13 D5 D12 D4 RESERVED D11 RESERVED D3 D2 D1 D0 ADC HPF BYP D10 D9 D8 7.5.28. Vendor ID1 and ID2 (Index 7Ch and 7Eh) These two registers contain four 8-bit ID codes. The first three codes have been assigned by Microsoft using their Plug and Play Vendor ID methodology. The fourth code is a SigmaTel, Inc. assigned code identifying the STAC9750/51. The ID1 register (index 7Ch) contains the value 8384h, which is the first (83h) and second (84h) characters of the Microsoft ID code. The ID2 register (index 7Eh) contains the value 7650h, which is the third (76h) of the Microsoft ID code, and 50h which is the STAC9750/51 ID code. Note: The lower half of the Vendor ID2 register (index 7Eh) currently contains the value xxh identifying the STAC9750/51. This value can be used by the audio driver, or miniport driver in the case of WIN98 (R) , to adjust software functionality to match the feature-set of the STAC9750/51. This portion of the register will likely contain different values if the software profile of the STAC9750/51 changes, as in the case of silicon level device modifications. This will allow the software driver to identify any required operational differences between the existing STAC9750/51 and any future versions. 7.5.28.1. Vendor ID1 (7Ch) Default: 8384h D15 1 D7 1 D14 0 D6 0 D13 0 D5 0 D12 0 D4 0 D11 0 D3 0 D10 0 D2 1 D9 1 D1 0 D8 1 D0 0 7.5.28.2. Vendor ID2 76xx (7Eh) Default: 7650h D15 0 D7 0 D14 1 D6 1 D13 1 D5 0 D12 1 D4 1 D11 0 D3 0 D10 1 D2 0 D9 1 D1 0 D8 0 D0 0 2-9750-D1- 5.3-0604 53 STAC9750/51 Value-Line Two-Channel AC'97 Codecs with Headphone Drive and SPDIF Output 8. LOW POWER MODES The STAC9750/51 is capable of operating at reduced power when no activity is required. The state of power down is controlled by the Powerdown Register (26h). There are 7 commands of separate power down. The power down options are listed in Table 44. The first three bits, PR0..PR2, can be used individually or in combination with each other, and control power distribution to the ADC's, DAC's and Mixer. The last analog power control bit, PR3, affects analog bias and reference voltages, and can only be used in combination with PR1, PR2, and PR3. PR3 essentially removes power from all analog sections of the codec, and is generally only asserted when the codec will not be needed for long periods. PR0 and PR1 control the PCM ADC's and DAC's only. PR2 and PR3 do not need to be "set" before a PR4, but PR0 and PR1 must be "set" before PR4. PR5 disables the internal codec clock and requires an external cold reset for recovery. PR6 disables the headphone driver amplifier for additional analog power saving. GRP Bits PR0 PR1 PR2 PR3 PR4 PR5 PR6 Function PCM in ADC's & Input Mux Powerdown PCM out DACs Powerdown Analog Mixer powerdown (VREF still on) Analog Mixer powerdown (VREF off) Digital Interface (AC-Link) powerdown (extnl clk off) Internal Clk disable Powerdown HEADPHONE_OUT Table 44. Low Power Modes The Figure 19 illustrates one example procedure to do a complete powerdown of STAC9750/51. From normal operation, sequential writes to the Powerdown Register are performed to power down STAC9750/51 a piece at a time. After everything has been shut off, a final write (of PR4) can be executed to shut down the AC-Link. The part will remain in sleep mode with all its registers holding their static values. To wake up, the AC'97 controller will send an extended pulse on the sync line, issuing a warm reset. This will restart the AC-Link (resetting PR4 to zero). The STAC9750/ 51 can also be woken up with a cold reset. A cold reset will reset all of the registers to their default states. When a section is powered back on, the Powerdown Control/ Status register (index 26h) should be read to verify that the section is ready (stable) before attempting any operation that requires it. PR0=1 PR1=1 PR2=1 PR4=1 Normal ADCs off PR0 DACs off PR1 Analog off PR2 or PR3 Digital I/F off PR4 Shut off AC-Link PR0=0 & ADC=1 PR1=0 & DAC=1 PR2=0 & ANL=1 Warm Reset Default Ready =1 Cold Reset Figure 19. Example of STAC9750/51 Powerdown/Powerup flow 54 2-9750-D1- 5.3-0604 STAC9750/51 Value-Line Two-Channel AC'97 Codecs with Headphone Drive and SPDIF Output Figure 20 illustrates a state when all the mixers should work with the static volume settings that are contained in their associated registers. This configuration can be used when playing a CD (or external LINE_IN source) through STAC9750/51 to the speakers, while most of the system in low power mode. The procedure for this follows the previous except that the analog mixer is never shut down. PR0=1 PR1=1 PR4=1 Normal ADCs off PR0 DACs off PR1 Digital I/F off PR4 Shut off AC-Link PR0=0 & ADC=1 PR1=0 & DAC=1 Warm Reset Figure 20. STAC9750/51 Powerdown/Powerup flow with analog still alive 2-9750-D1- 5.3-0604 55 STAC9750/51 Value-Line Two-Channel AC'97 Codecs with Headphone Drive and SPDIF Output 9. MULTIPLE CODEC SUPPORT The STAC9750/51 provides support for the multi-codec option according to the Intel AC'97, rev 2.2 specification. By definition there can be only one Primary Codec (Codec ID 00) and up to three Secondary Codecs (Codec IDs 01,10, and 11). The Codec ID functions as a chip select. Secondary devices therefore have completely orthogonal register sets; each is individually accessible and they do not share registers. 9.1. Primary/Secondary Codec Selection In a multi-codec environment the codec ID is provided by external programming of pins 45 and 46 (CID0 and CID1). The CID pin electrical function is logically inverted from the codec ID designation. The corresponding pin state and its associated codec ID are listed in the "Codec ID Selection" table. Also see slot assignment discussion, "Multi-Channel Programming Register (Index 74)". CID1 State Dvdd or floating Dvdd or floating 0V 0V CID0 State Dvdd or floating 0V Dvdd or floating 0V Codec ID 00 01 10 11 Codec Status Primary Secondary Secondary Secondary Table 45. Codec ID Selection 9.1.1. Primary Codec Operation As a Primary device the STAC9750/51 is completely compatible with existing AC'97 definitions and extensions. Primary Codec registers are accessed exactly as defined in the AC'97 Component Specification and AC'97 Extensions. The STAC9750/51 operates as Primary by default, and the external ID pins (45 and 46), have internal pull-ups so that these pins may be left as no-connects for primary operation. When used as the Primary Codec, the STAC9750/51 generates the master AC-Link BIT_CLK for both the AC'97 Digital Controller and any Secondary Codecs. The STAC9750/51 can support up to 4, 10 K 50 pF loads on the BIT_CLK. This is to insure that up to 4 Codec implementations will not load down the clock output. 9.1.2. Secondary Codec Operation When the STAC9750/51 is configured as a Secondary device the BIT_CLK pin is configured as an input at power up. Using the BIT_CLK provided by the Primary Codec insures that everything on the AC-Link will be synchronous. As a Secondary device it can be defined as Codec ID 01, 10, or 11 in the two-bit field(s) of the Extended Audio and/or Extended Modem ID Register(s). 56 2-9750-D1- 5.3-0604 STAC9750/51 Value-Line Two-Channel AC'97 Codecs with Headphone Drive and SPDIF Output 9.2. Secondary Codec Register Access Definitions The AC'97 Digital Controller can independently access Primary and Secondary Codec registers by using a 2-bit Codec ID field (chip select) which is defined as the LSBs of Output Slot 0. For Secondary Codec access, the AC'97 Digital Controller must invalidate the tag bits for Slot 1 and 2 Command Address and Data (Slot 0, bits 14 and 13) and place a non-zero value (01, 10, or 11) into the Codec ID field (Slot 0, bits 1 and 0). As a Secondary Codec, the STAC9750/51 will disregard the Command Address and Command Data (Slot 0, bits 14 and 13) tag bits when it sees a 2-bit Codec ID value (Slot 0, bits 1 and 0) that matches its configuration. In a sense the Secondary Codec ID field functions as an alternative Valid Command Address (for Secondary reads and writes) and Command Data (for Secondary writes) tag indicator. Secondary Codecs must monitor the Frame Valid bit, and ignore the frame (regardless of the state of the Secondary Codec ID bits) if it is not valid. AC'97 Digital Controllers should set the frame valid bit for a frame with a secondary register access, even if no other bits in the output tag slot except the Secondary Codec ID bits are set. This method is designed to be backward compatible with existing AC'97 controllers and Codecs. There is no change to output Slot 1 or 2 definitions. Output Tag Slot (16-bits) Bit 15 14 13 12-3 2 1-0 Note: Description Frame Valid Slot 1 Valid Command Address bit (Primary Codec only) Slot 2 Valid Command Data bit (Primary Codec only) Slot 3-12 Valid bits as defined by AC'97 Reserved (Set to "0") 2-bit Codec ID field (00 reserved for Primary; 01, 10, 11 indicate Secondary) New definitions for Secondary Codec Register Access Table 46. Secondary Codec Register Access Slot 0 Bit Definitions 2-9750-D1- 5.3-0604 57 STAC9750/51 Value-Line Two-Channel AC'97 Codecs with Headphone Drive and SPDIF Output 10.TESTABILITY The STAC9750/51 has two test modes. One is for ATE in-circuit test and the other is restricted for SigmaTel's internal use. STAC9750/51 enters the ATE in circuit test mode if SDATA_OUT is sampled high at the trailing edge of RESET#. Once in the ATE test mode, the digital AC-Link outputs (BIT_CLK and SDATA_IN) are driven to a high impedance state. This allows ATE in-circuit testing of the AC'97 controller. Use of the ATE test mode is the recommended means of removing the codec from the AC-Link when another codec is to be used as the primary. This case will never occur during standard operating conditions. Once either of the two test modes have been entered, the STAC9750/51 must be issued another RESET# with all AC-link signals held low to return to the normal operating mode. 58 2-9750-D1- 5.3-0604 STAC9750/51 Value-Line Two-Channel AC'97 Codecs with Headphone Drive and SPDIF Output 11.PIN DESCRIPTION MONO_OUT AVdd2 HP_OUT_L HP_COMM HP_OUT_R AVss2 GPIO0 GPIO1 CID0 CID1 EAPD SPDIF 37 38 39 40 41 42 43 44 45 46 47 48 36 35 34 33 32 31 30 29 28 27 26 25 LINE_OUT_R LINE_OUT_L NC NC CAP2 NC AFILT2 AFILT1 VREFout VREF AVss1 AVdd1 48-Pin TQFP 24 23 22 21 20 19 18 17 16 15 14 13 LINE_IN_R LINE_IN_L MIC2 MIC1 CD_R CD_GND CD_L VIDEO_R VIDEO_L AUX_R AUX_L PHONE Figure 21. STAC9750/51 Pin Description Drawing Pin 48: To Enable SPDIF, use an 1K-10K external pulldown. To Disable SPDIF, use an 1K-10K external pullup. Do Not leave Pin 48 floating. The CD_GND signal is an AC signal return for the two CD input channels. It is normally biased at about 2.5V. The name of the pin in the AC97 specification is CD_GND, and this has confused many designers. It should not have any DC path to GND. Connecting the CD_GND signal directly to ground will change the internal bias of the entire codec, and cause bad distortion. If there is no analog CD input, then this pin can be No-Connect 2-9750-D1- 5.3-0604 DVdd1 1 XTL_IN 2 XTL_OUT 3 DVss1 4 SDATA_OUT 5 BIT_CLK 6 DVss2 7 SDATA_IN 8 DVdd2 9 SYNC 10 RESET# 11 PC_BEEP 12 59 STAC9750/51 Value-Line Two-Channel AC'97 Codecs with Headphone Drive and SPDIF Output 11.1. Digital I/O These signals connect the STAC9750/51 to its AC'97 controller counterpart, an external crystal, multi-codec selection and external audio amplifier. Pin Name XTL_IN XTL_OUT SDATA_OUT BIT_CLK SDATA__IN SYNC RESET# NC NC NC GPIO0 GPIO1 CID0 CID1 EAPD SPDIF Pin # 2 3 5 6 8 10 11 31 33 34 43 44 45 46 47 48 Type I I/O I I/O O I I I/O I/O I/O I/O I/O I I I/O O Description 24.576 MHz Crystal or External Clock Source 24.576 MHz Crystal or ground if external clock source connected to XTAL_IN Serial, time division multiplexed, AC'97 input stream 12.288 MHz serial data clock Serial, time division multiplexed, AC'97 output stream 48 kHz fixed rate sample sync AC'97 Master H/W Reset No Connect No Connect No Connect General Purpose I/O General Purpose I/O Multi-Codec ID select - bit 0 Multi-Codec ID select - bit 1 External Amplifier Power Down SPDIF digital output Pin 48: To Enable SPDIF, use an 1K-10K external pulldown. To Disable SPDIF, use an 1K-10K external pullup. Do Not leave Pin 48 floating. Table 47. Digital Connection Signals 60 2-9750-D1- 5.3-0604 STAC9750/51 Value-Line Two-Channel AC'97 Codecs with Headphone Drive and SPDIF Output 11.2. Analog I/O These signals connect the STAC9750/51 to analog sources and sinks, including microphones and speakers. Pin Name PC-BEEP PHONE AUX_L AUX_R VIDEO_L VIDEO_R CD_L CD_GND CD_R MIC1 MIC2 LINE_IN_L LINE_IN_R LINE_OUT_L LINE_OUT_R MONO_OUT HP_OUT_L HP_COMM HP_OUT_R Pin # 12 13 14 15 16 17 18 19 20 21 22 23 24 35 36 37 39 40 41 Type I* I* I* I* I* I* I* I* I* I* I* I* I* O O O O O O Description PC Speaker beep pass-through From telephony subsystem speakerphone (or DLP:Down Line Phone) Aux Left Channel Aux Right Channel Video Audio Left Channel Video Audio Right Channel CD Audio Left Channel CD Audio analog ground CD Audio Right Channel Desktop Microphone Input Second Microphone Input Line In Left Channel Line In Right Channel Line Out Left Channel Line Out Right Channel To telephony subsystem speakerphone(or DLP - Down Line Phone) Headphone Out Left Channel Headphone Ground Return Headphone Out Right Channel Table 48. Analog Connection Signals Note: * any unused input pins should be tied together through a capacitor (0.1 F suggested) to ground, except the MIC inputs which should have their own capacitor to ground if not used. The CD_GND signal is an AC signal return for the two CD input channels. It is normally biased at about 2.5V. The name of the pin in the AC97 specification is CD_GND, and this has confused many designers. It should not have any DC path to GND. Connecting the CD_GND signal directly to ground will change the internal bias of the entire codec, and cause bad distortion. If there is no analog CD input, then this pin can be No-Connect 2-9750-D1- 5.3-0604 61 STAC9750/51 Value-Line Two-Channel AC'97 Codecs with Headphone Drive and SPDIF Output 11.3. Filter/References/GPIO These signals are connected to resistors, capacitors, specific voltages, or provide general purpose I/O. Signal Name VREF VREFOUT AFILT1 AFILT2 CAP2 Pin Number 27 28 29 30 32 Type O O O O O Description Analog ground (.45*vdd, at 5V; .41*vdd at 3V) Reference Voltage out 5mA drive (intended for mic bias) (~vdd/2) Anti-Aliasing Filter Cap - ADC left channel Anti-Aliasing Filter Cap - ADC right channel ADC reference Cap Table 49. Filtering and Voltage References 11.4. Power and Ground Signals Pin Name AVdd1 AVdd2 AVss1 AVss2 DVdd1 DVdd2 DVss1 DVss2 Pin # 25 38 26 42 1 9 4 7 Type I I I I I I I I Analog Vdd = 5.0V or 3.3V Analog Vdd = 5.0V or 3.3V (headphone power source) Analog Gnd Analog Gnd Digital Vdd = 3.3V Digital Vdd = 3.3V Digital Gnd Digital Gnd Description Table 50. Power and Ground Signals 62 2-9750-D1- 5.3-0604 STAC9750/51 Value-Line Two-Channel AC'97 Codecs with Headphone Drive and SPDIF Output 12.PACKAGE DRAWING D D1 26 38 a e E E1 48 pin TQFP 14 2 Figure 22. 48-Pin TQFP Package Drawing Key D D1 E E1 a (lead width) e (pitch) thickness TQFP Dimensions 9.00 mm 7.00 mm 9.00 mm 7.00 mm 0.20 mm 0.50 mm 1.4 mm Table 51. 48-Pin TQFP Package Dimensions 2-9750-D1- 5.3-0604 63 STAC9750/51 Value-Line Two-Channel AC'97 Codecs with Headphone Drive and SPDIF Output 13.APPENDIX A: SPLIT INDEPENDENT POWER SUPPLY OPERATION In PC applications, one power supply input to the STAC9750/51 may be derived from a supply regulator (as shown in Figure 23) and the other directly from the PCI power supply bus. When power is applied to the PC, the regulated supply input to the IC will be applied some time delay after the PCI power supply. Without proper on-chip partitioning of the analog and digital circuitry, some manufacturer's codecs would be subject to on-chip SCR type latch-up. SigmaTel's STAC9750/51 specifically allows power-up sequencing delays between the analog (AVddx) and digital (VDddx) supply pins. These two power supplies can power-up independently and at different rates with no adverse effects to the codec. The IC is designed with independent analog and digital circuitry that prevents on-chip SCR type latch-up. 64 2-9750-D1- 5.3-0604 STAC9750/51 Value-Line Two-Channel AC'97 Codecs with Headphone Drive and SPDIF Output 3.3V or 5V 5% *Suggested 3.3V 5% 0.1 F 1 F 0.1 F 0.1 F 10 F 0.1 F 25 AVdd1 38 AVdd2 1 DVdd1 9 DVdd2 XTL_IN 2 27 pF 12 PC_BEEP 13 PHONE SDATA_OUT 14 AUX_L 15 AUX_R 16 VIDEO_L RESET# 17 VIDEO_R 18 CD_L 19 CD_GND 20 CD_R VREF 21 MIC1 22 MIC2 23 LINE_IN_L 24 LINE_IN_R *OPTIONAL 32 CAP2 GPIO1 0.1 F 1 F* GPIO0 LINE_OUT_L 820 pF 29 AFILT1 LINE_OUT_R MONO_OUT AFILT2 HP_OUT_L 39 41 HP_COMM NC NC NC SPDIF 31 33 34 48 40 44 43 35 36 37 VREFOUT 28 27 CID1 EAPD BIT_CLK SDATA_IN SYNC 5 6 8 10 11 45 46 47 XTL_OUT 3 24.576 MHz 27 pF 22 EMI Filter 27 pF OPTIONAL STAC9750 CID0 *OPTIONAL 0.1 F 1 F* 820 pF 30 AVss1 26 AVss2 42 DVss1 4 DVss2 7 HP_OUT_R *Terminate ground plane as close to codec as possible Analog Ground Digital Ground Figure 23. STAC9750/51 Split Independent Power Supply Operation Typical Connection Diagram Pin 48: To Enable SPDIF, use an 1K-10K external pulldown. To Disable SPDIF, use an 1K-10K external pullup. Do Not leave Pin 48 floating. 2-9750-D1- 5.3-0604 65 STAC9750/51 Value-Line Two-Channel AC'97 Codecs with Headphone Drive and SPDIF Output 14.APPENDIX B: PROGRAMMING REGISTERS Reg # Name D15 D14 00h Reset RSRVD SE4 02h Master Volume Mute RSRVD HP_OUT Mixer Volume Master Volume 06h Mono PC_BEEP 0Ah Volume 0Ch Phone Volume 04h 0Eh 10h 12h 14h 16h 18h 1Ah 1Ch 20h Mic Volume Line In Volume CD Volume Video Volume AUX Volume PCM Out Volume Record Select Record Gain General Purpose Mute Mute Mute Mute Mute Mute Mute Mute Mute Mute RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RSRVD 3D GL4 GL4 GL4 GL4 GL4 RSRVD D13 SE3 ML5 HPL5 D12 SE2 ML4 HPL4 D11 SE1 ML3 HPL3 D10 SE0 ML2 HPL2 D9 ID9 ML1 HPL1 D8 ID8 ML0 HPL0 D7 D6 ID7 ID6 RESERVED RESERVED D5 ID5 MR5 HPR5 MM5 D4 ID4 MR4 HPR4 MM4 PV3 GN4 GL0 GL0 GL0 GL0 GL0 SL0 GL0 MS LPBK boosted RSRVD RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED GN4 GR4 GR4 GR4 GR4 GR4 D3 ID3 MR3 HPR3 MM3 PV2 GN3 GN3 GR3 GR3 GR3 GR3 GR3 D2 ID2 MR2 HPR2 MM2 PV1 GN2 GN2 GR2 GR2 GR2 GR2 GR2 SR2 GR2 D1 ID1 MR1 HPR1 MM1 PV0 GN1 GN1 GR1 GR1 GR1 GR1 GR1 SR1 GR1 D0 ID0 MR0 HPR0 MM0 Default 6990h 8000h 8000h 8000h RESERVED RESERVED RESERVED RESERVED GL3 GL2 GL3 GL2 GL3 GL2 GL3 GL3 GL2 GL2 SL2 GL2 GL1 GL1 GL1 GL1 GL1 SL1 GL1 MIX RESERVED I3 PR6 ID0 RESERVED PR5 PR4 I0 PR3 REV1 (0) PR2 REV0 (1) SPCV SR11 SR11 L SR10 SR10 CC6 SR9 SR9 CC5 PR1 AMAP PR0 LDAC SDAC RSRVD 0000h GN0 GN0 GR0 GR0 GR0 GR0 GR0 SR0 GR0 8008h 8008h 8808h 8808h 8808h 8808h 8808h 0000h 8000h 0000h Mute POP BYP GL3 RESERVED GR3 RESERVED DP3 22h 3D Control 24h** Audio Interrupt I4 Powerdown 26h EAPD Ctrl/Stat Extended 28h ID1 Audio ID Extended 2Ah Audio Control/ Status PCM DAC 2Ch SR15 Rate PCM LR 32h SR15 ADC Rate 3Ah 3Eh** 4Ch** 4Eh** 50h** 52h** SPDIF Control Extended Modem Status GPIO Pin Config GPIO Pin Polarity/Type GPIO Pin Sticky #V DP2 RESERVED RESERVED RESERVED CDAC DSA1 DSA0 REF RSVD ANL SPDIF DAC DRA ADC VRA 0000h 0000h 000Fh 0605h RESERVED RESERVED RSRVD SR8 SR8 CC4 PRA RESERVED RESERVED RESERVED RESERVED RESERVED SR7 SR7 CC3 SR6 SR6 CC2 VRA SPSA1 SPSA0 RSRVD SPDIF RSRVD enable 0400h SR5 SR5 CC1 SR4 SR4 CC0 RESERVED SR3 SR3 PRE SR2 SR2 SR1 SR1 SR0 SR0 PRO GPIO BB80h BB80h 2A00h 0100h SR14 SR14 DRS SR13 SR13 SR12 SR12 SPSR1 SPSR2 RESERVED COPY #PCM/ AUDIO GC1 GC0 0300h (GPIO1) (GPIO0) GP1 GP0 FFFFh (GPIO1) (GPIO0) GS1 GS0 (GPIO1) (GPIO0) 0000h GW1 GW0 0000h (GPIO1) (GPIO0) GI1 GI0 0000h (GPIO1) (GPIO0) RESERVED GR4 GR3 GR2 GR1 DO1 0 0 0 0 0 MUTE ADCslot ADCslot FIX RSVD 1 0 DISBLE EN6 EN5 EN4 EN3 RESERVED RESERVED EN7 EN6 EN5 EN4 EN3 EN2 EN1 EN0 ADC HPF BYP 0 0 0 MIC GAIN VALUE EN2 0 SPLY OVR EN EN1 GR0 DO0 0 SPLY OVR VAL EN0 RSVD 8808h 0000h 00xxh 1000h 0000h 0000h 0000h 0000h 0000h 8384h 7650h GPIO Pin Mask GPIO Pin 54h** Status Z_DATA 60h Volume Digital Audio 6Ah Control 6Ch Revision Code 6Eh 70h 72h 74h* 76h 78h 7Ch 7Eh Analog Special Mute RESERVED GL4 GL3 GL2 GL1 GL0 RESERVED 0 0 RESERVED EN14 EN13 0 0 AC97 ALL MIX EN12 0 0 0 RESERVED EN11 EN10 EN9 EN8 EN7 INT APOP 0 72h Enable EN15 Analog Current Adjust GPIO Access EAPD 78h Enable High Pass Filter Bypass Vendor ID1 Vendor ID2 9750 1 0 EN15 RESERVED RSVD EN14 EAPD_ RESER GPIO1_ GPIO0_ GPIO1 GPIO0 OEN VED OEN OEN EN13 EN12 EN11 EN10 EN9 EN8 IBIAS<1:0> RSESERVED 0 1 0 1 0 1 0 0 0 1 1 1 1 0 1 0 0 1 0 0 0 1 0 0 1 0 0 0 Note: 1. 2. 3. 4. 66 All registers not shown and those labeled "RESERVED" can be written to but are don't care upon read back. PC_BEEP default to 0000h, mute off Register 74h is used for GPIO control in revision CA3. **Registers used in revision CC1 and beyond for GPIO. EAPD is still controled by Register 74. 2-9750-D1- 5.3-0604 STAC9750/51 Value-Line Two-Channel AC'97 Codecs with Headphone Drive and SPDIF Output 15.DOCUMENT HISTORY Prior to Rev 5.1 -- History not included in Datasheet Rev 5.2 (October 2003) 1. Corrected error on page 26: Slot 1 Status Address Port, bit D2 is a SLot Request not reserved as stated in rev 5.1 2. Added CD_GND elaboration note on connection diagram, pin list and pin out diagrams: The CD_GND signal is an AC signal return for the two CD input channels. It is normally biased at about 2.5V. The name of the pin in the AC97 specification is CD_GND, and this has confused many designers. It should not have any DC path to GND. Connecting the CD_GND signal directly to ground will change the internal bias of the entire codec, and cause bad distortion. If there is no analog CD input, then this pin can be No-Connect. Rev 5.3 (June 2004) corrected Note 4 in performance characteristics, was missing the text "Ratio of Full Scale signal toTHD+N output with -3dB signal, measured "A weighted" over a". Complete note now reads "Ratio of Full Scale signal toTHD+N output with -3dB signal, measured "A weighted" over a 20 Hz to a 20 kHz bandwidth. 48 kHz Sample Frequency". 2-9750-D1- 5.3-0604 67 |
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